ITRS Test ITWG

1. ITRS Test ITWG July 2004

2. Acknowledgements • ITWG Members • Rochit Rajsuman (Advantest), Yi Cai (Agere), Bill Ortner (Agere), Rob Aitken (Artisan), Atul Goel (Agilent), Peter Maxwell (Agilent), Bernd Koenemann (Cadence), Anne Gattiker (IBM), Phil Nigh (IBM), Fred Taber (IBM), Jody Van Horn (IBM), Don Wheater (IBM), Peter Muhmenthaler (Infineon), Phil Burlison (Inoys), Roger Barth (Intel), Don Edenfeld (Intel), Mike Rodgers (Intel), Chad Wren (Intel), Yasumasa Nishimura (Renesas), Jay Bedsole (Motorola), Paul Roddy (Motorola), Don Van Overloop (Motorola), Toshinobu Ono (NEC), Burnie West (NPTest), Bill Price (Philips), Rene Segers (Philips), Tom Williams (Synopsys), Lee Song (Teradyne), Yervant Zorian (Virage) • Contributors • Davide Appello (ST Microelectronics), John Johnson (Intel), John Matthias (Agere), Lynn Schmidt (Agilent), Marc Loranger (Credence), Michael Lee (TSMC), Rudy Garcia (NPTest), Bernd Laquai (Agilent), Sunil Jain (Intel), Udaya Natarajan (Intel), Mike Green (Motorola), Charles Ross (Motorola), John Ferrario (IBM), Dennis Eaton (Agilent), Paul Nesrsta (Rel Inc), Rich Karr (TI), Jim Rhodes (Unisys), Ichiro Fujishiro (Yamaichi), Gordon Cowan (High Rel), Ken Heiman (MCC), Dave Noddin (3M), Herve Deshayes (ST Micro), Dick McClelland (Philips), Carl Buck (Aehr Test), Rafiq Hussain (AMD), Dan Weinstein (Intel), Bob Totorica (Micron), Bob Zacharis (Pycon), John Hartstein (Wells-CTI), Takashi Aikyo, Kenichi Anzou, Kouichi Eguchi, Satoshi Fukumoto, Kazumi Hatayama, Toshinori Inoshita, Shinji Mori, Mitsuyasu Ohta, Akira Ooishi, Masayuki Sato, Hidefumi Toda, Masanori Ushikubo, Osamu Yamada, Chip Cotton (Intel), Dan Sech (Intel), Brett Casey (Intel), Sematech Product Analysis Forum (Larry Wagner (IT), Dave Vallett (IBM)), Stefan Eichenberger (Philips), Ted Lundquist (NPtest), HankWalker (TX A&M), Bob Madge (LSI Logic), Camelia Hora (Philips Research), Maurice Lousberg (Philips Research) Many Thanks!

3. 2004 Spring ITRS Workshop - Outcomes April 2004 Stressa, Italy

4. Attendees • Rene Segers, Philips • Robert van Rijsinge, Philips • Peter Muhmenthaler, Infineon • Davide Appello, ST Microelectronics • Tom Williams, Synopsys • Burnie West, NPTest • Don Edenfeld, Intel • Anzou-san, Toshiba, DFT SWG • Noguchi-san, NECEL, ATE SWG

5. Roadmap Plans • 2004 Update • Minor changes to most tables • Increased focus on analog/RF table, introduction of power device requirements • 2005 Revision • Reliability Screens • Merge of logic tables • Merge embedded memory with SOC • Addition of EDA DFT tools and DFx content • Addition of test & burn-in sockets and test interface boards

6. Cross-TWG Outcomes • Assembly & Packaging • New package technologies have potential impact on test, requires further evaluation • Factory Integration • Further dialog on intelligent yield management systems to support increases use of adaptive test • Design • Further discussion required to close on handling of DFT content of the roadmap – what & where • Interconnect • Increasing delay on local interconnect will have a dramatic impact on test methods – requires further evaluation • Yield Enhancement • Not on Spring schedule, but need dialog

7. 2003 Results

8. 2003 ITRS Test Chapter Revision • Trends described in 2001 have held true • High speed interfaces are appearing in a broad range of applications in many market segments • SOC and SIP dominate new designs • Low cost, targeted test platforms emerging • 2003 Test Chapter focuses on key challenges • Less emphasis on evolutionary trending • Increased effort to identify, define, and discuss the key challenges facing test

9. Chapter Content Additions • Test Technology Requirements • Test and Yield Learning • Physical Failure Analysis • Software-Based Diagnosis and Signature Analysis • Defects and Failure Mechanisms • Reliability Technology Requirements • IDDQ Testing • Burn-In Requirements • Test Handler and Prober Technology Requirements • Test Handlers • Wafer Probers • Device Interface Technology Requirements • Probe Cards

10. 2003 Key Challenges • High Speed Device Interfaces • Highly Integrated Designs, SOCs, & SIPs • Reliability Screens • Manufacturing Test Cost Reduction • Failure Analysis and Diagnosis • Automated Test Program Generation (not ATPG!) • Modeling and Simulation

11. High Speed Serial Interfaces • Penetration of high speed interfaces into new designs is increasing dramatically • Leading edge communications devices data rate trend slowing, but … • High speed links (1.5 to 4 Gbps, 10s to 100s) dropping into many other product types / business segments / formerly plain vanilla digital products • Loopback alone may not be sufficient to achieve needed product quality • Transaction / event driven protocols inconsistent with stored response ATE / mfg test • Test and DFT methods must be developed to enable development and production test of these products

12. SOC and SIP • Customer requirements for form factor and power consumption are driving a significant increase in design integration levels • Test complexity will increase dramatically with the combination of different classes of circuits on single die or within a single package • Disciplined, structured DFT is a requirement to reduce test complexity • Increased focus on KGD and sub-assembly test driven by cost for SIP • Mems, opticals, and other emerging or newly integrated to SIP devices • SIP physical FA is much more difficult, test diagnostics will be critical • Manufacturing repair may be required for non-stacked die SIPs

13. BISR/BIRA Path Delay Test Strategy Analog Isolation BOST Scan+ATPG IP Core Isolation BIST Analog DSP Control Memory Logic MCU IP Core Based Design Test Implications of IP Design • Test Strategy and Integration • DFT for IP Core Based Design • Higher Level DFT • Standardization

14. IP Core Test Wrapper Insertion SoC Test Wrapper DFT DFT Test Data Test Data Conversion Test Controller Chip-Level Test Data Configuration of Chip-Level Test Controller and Test Access Mechanism Automated DFT Insertion • Automation of test control integration and test scheduling • Insert test wrapper and test control circuits

15. Reliability Screens Run Out of Gas • Critical need for development of new techniques for acceleration of latent defects • Burn-in methods limited by thermal runaway • Lowered use voltages limits voltage stress opportunity • Difficulty of determining Iddq signal versus “normal” leakage current noise • New materials • Rate of introduction increasing: Cu, low k, high k, SiGe • Critical interactions of new materials increasing (Cu / low k) • Increasing mechanical and thermal sensitivities

16. The Overall Cost of Test $ NRE Costs $ DFT design and validation $ Test development $ Device Costs $ Die area increase $ Yield loss $ Work-Cell Cost $ Building Capital $ People $ Consumables $ Loadboards, DUT interface $ Capital Equipment Depreciation of: $ Test Equipment $ Handler/Prober Work-Cell Good Units Shipped Untested Units • Goal is to optimize product cost • Must strike a balance between cost of design, manufacture, and test UPH/$M Effectiveness Measure Rejected Units

17. Test Capability Treadmill • DFT and test methods development is effectively constraining logic test requirements • Capability driven investment into equipment for testing Analog, RF, and SerDes circuits • SiP and SoC drive convergence of leading edge, high density logic with flash, DRAM, SRAM, analog, RF, and SerDes • The move toward open architecture is intended to make it easier (and cheaper) to implement incremental capability while enabling reuse

18. Failure Analysis and Diagnosis • Enhanced automated software diagnostic capabilities to improve physical failure analysis ROI • Characterization capabilities must identify, locate, and distinguish individual defect types • Increased accuracy and throughput (days to hours) • Failure analysis methods for analog devices must be developed • DFT is essential to localize failures • Improve efficiency and reduce design complexities associated with test • Defect types and behavior will continue to evolve with advances in fabrication process technology • Fundamental research in existing and novel fault models to address emerging defects will be required

19. Automated Test Program Generation • Tools for ATE software and test program generation are needed to decrease test development effort and improve time to market • Automated design to manufacturing test program flow • Correct by construction (pre-silicon) • Interoperability standards (STIL, CTL, etc) • Enable test content portability among test platforms • ATE S/W operating environment standards • Direct impact on time to market and product development cost • Driven by product complexity and shorter product cycles

20. Modeling and Simulation • Signal Integrity and Power Delivery • High speed signals, increasing analog content, and high power designs drive more rigorous interface design • Modeling of the complete path • Device I/O • Probe or Package + Socket • ATE interface hardware • ATE instrumentation or power supply