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ITRS Design + System Drivers December 3, 2010 Design ITWG PowerPoint Presentation
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ITRS Design + System Drivers December 3, 2010 Design ITWG

ITRS Design + System Drivers December 3, 2010 Design ITWG

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ITRS Design + System Drivers December 3, 2010 Design ITWG

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  1. ITRS Design + System DriversDecember 3, 2010Design ITWG • Software, system level design productivity critical to roadmap • 2. Manufacturability  variability  reliability  resilience • 3. Design cost will be contained through innovation • 4. Design power must also be contained through innovation! • 5. 2011 improvements focus on Verification, SOC (vs. SIP) and AMS/RF System Drivers, and Cross-TWG improvements

  2. 2010 Overview (2004-Today)1. Increasingly quantitative roadmap2. Increasingly complete driver set 2009 MTM RF+AMS Driver Updated Consumer SOC and MPU Drivers Upgraded RF+AMS section 2008 MTM extension + iNEMI synch + SW !! MTM extension + iNEMI + SW !! 2007 More Than Moore (MTM) analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter

  3. Design / System Drivers 2010*-2011* Plans • Design chapter • Improve design productivity and cost models * • Develop “Design Power Chart” similar to Design Cost Chart * • Ensure 3D / TSV content consistent with other chapters * • Improve DFM section, including Design for Reliability * • Overhaul of Verification *, Logic/Circuit/Physical sections * • System Drivers chapter • Flatten MPU frequency roadmap, evaluate impact * • Update of SOC-CP and SOC-CS models (driven from TWGs) * • Update AMS/RF Driver / fabric with Wireless TWG * • More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) * • Other Cross-TWG and public activity • PIDS: increase design-driven requirements definition * • 3D/TSV: hold for ACTION * • Continue key interactions: A&P, Interconnect, Test * • Gather input from 2nd EDA Roadmap Workshop (@DAC)*

  4. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

  5. 2010 Updated Charts Design Productivity and COST RTL Functional Verif. Tool Suite System Design Automation Transaction Level Modeling IC Implementation Tool Set Many Core Devel. Tools Executable Specification SMP Parallel Processing AMP Parallel Processing Software Virtual Prototype Silicon Virtual Prototype Very Large Block Reuse Intelligent Testbench Concurrent Memory Figure DESN1 -- Impact of Design Technology on SoC SOC Consumer Portable Implementation Cost

  6. 2010 Updated Charts SOC-CP Complexity

  7. 2010 Updated Charts SOC-CP Power

  8. 2010 Updated Charts SOC-CP Performance

  9. 2010 Updated Charts SOC-CS Number of Cores and Performance Figure SYSD9

  10. 2010 Updated Charts SOC-CS Number of DPEs and Performance Figure SYSD10

  11. 2010 Updated Charts SOC-Stationary Power Figure SYSD11

  12. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

  13. 2001-2010: Design Cost Roadmap Design Cost $ SOFTWARE HARDWARE YEAR

  14. 2001-2010: Design Cost Roadmap Design Productivity INNOVATIONS RTL Functional Verif. Tool Suite System Design Automation Transaction Level Modeling IC Implementation Tool Set AMP Parallel Processing Executable Specification SMP Parallel Processing Many Core Devel. Tools Very large block reuse Transactional Memory Intelligent Testbench Design Cost $ SOFTWARE HARDWARE YEAR

  15. 2011+: Design Power Management Roadmap ESTIMATION GATING DVFS MULTI-VDD MULTI-VT,CD GALS/ASYNC 3D / TSV RESILIENCE BTWC POWER DIST ENERGY-PROP SIGNOFF HW ACCEL

  16. Basis for quantifying ITRS Grand Challenges Productivity  Power 2003: Low-Power SOC proposal 2005: Consumer Portable SOC power analysis 2006: Consumer Stationary SOC power analysis 2007: Productivity impact of low-power design 2008/9: Changes to devices, densities 2010+: Roadmap challenges increasingly organized around Power instead of Productivity Future update of SOC Driver will comprehend heterogeneity, power management, applications, memory and communication architectures Core Effort: STRJ-WG1 SOC Modeling

  17. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

  18. Key Challenges in Digital Verification • STRJ WG1 study in 2010 • Scope: HW functional verification (functional spec through RTL), high-level performance verification • 8 Key Problems identified • Structure: Status, Problem, Challenges, Near-/Long-Term Solutions Optimized verification planning Verification Strategy Planning Develop expert human resource Definite specification without misunderstanding Exhaustive extraction of to-be-verified items, and optimized verification process Specification Design IP model preparation and quality verification High-speed simulation Verification Execution Efficient debugging Equivalence check for C to RTL

  19. Example: Develop Expert Human Resource • Current Status(2010) • Few engineers can develop UVM verification environment • Many engineers can use assertions for dynamic simulation, but formal verification is too difficult for most engineers • Training of verification engineers is local, not methodical • Problem Statement • Need new skills for new methodologies such as formal verification • Few engineers can handle many kinds of verification methodologies • Challenges • Scarcity of skilled verification engineers  increasing TAT and declining design quality • Near-Term Solutions • Implement human resources program for verification, e.g., promoting a guideline for IP verification • Long-Term Solutions • System for developing verification engineers, understanding how different kinds of skills are learned, and how to measure skills

  20. Example: Vendor IP Model Preparation and Quality Verification • Current Status(2010) • No IP guarantee quality • Must add testbench if not sufficiently provided by IP vendor • Both black-box and white-box IP distributed • Problem Statement • No system that can guarantee quality of IP • No standard for IP models; each IP vendor has different deliverables • Difficult to check quality of black-box IP • Challenges • Cannot measure quality of IP and deliverables without common quality criteria • Cost and time to develop additional functional models or testbenches • Product teams extremely nervous about quality • Near-Term Solutions • Internal IP design review • Internal IP quality checks • Make unused functions explicit • Long-Term Solutions • Institutionalize certification of standards-compliant IP quality • Guideline for IP deliverables (files/contents, must/should/could)

  21. Example: Efficient Debugging • Current Status(2010) • Assertions and formal verification are used • “Schematic viewer” type debug tools are popular and widely applied. “Lint” type tools produce many pseudo-errors.  steady human effort is of fundamental importance • Problem Statement • Assertion methods not widespread because designers are unfamiliar with methods • Prioritizing extracted errors and how to resolve depends on skill of verification engineer • Challenges • Efficiency in debugging is not improved • Efficiency and quality of debugging varies widely depending on engineers’ skills • Near-Term Solutions • Automated assertion tool and support by EDA vendors • Compilation of know-how for debugging, and sharing to designers through training • Long-Term Solutions • Reusable assertions as verification IP ( know-how can be applied by automated tools) • Verification IP and Verification Bench must be reusable  faster setup of verification environment, greater debug efficiency

  22. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

  23. Design and System DriversITRS-iNEMI Domain Space iNEMI (emulators) Market requirements ITRS (Drivers) Tech requirements Chip level System level

  24. New System Drivers? At the right pace… • Is SIP a new fabric ? • What application is the right driver for (leading edge) 3D/TSVs ? 2010? 2010? 2007 2006 2006 2006 2010? Fabrics ? MPU SIP PE/DSP Memory AMS Markets Consumer Stationary Consumer Portable Medical Automotive Network Office A&D

  25. ITRS-iNEMI Domain Space SiP-SoC More-than-Moore Proposal Chip level System level Market requirements Portable emulator Portable consumer driver Tech requirements 1 2 3 RF/AMS Driver Update portable driver Update portable emulator PA Case Study (SoC v. SiP)

  26. Equivalent cost = NRE + non-NRE per-board cost ITRS-iNEMI MTM SOC/SIP Design/IntegrationUpdate of ITRS and iNEMI Portable Drivers Inclusion of AMS/RF sub-driver from ITRS AMS driver PA Case Study Power (SiP) Power (SoC) Equivalent cost (SoC) Other AMS Equivalent cost (SiP) PA (RF)

  27. Equivalent cost = NRE + non-NRE per-board cost An Alternative Driver  Tuner / Demodulator Inclusion of AMS/RF sub-driver from ITRS AMS driver Tuner-demod case Study Power (SiP) Power (SoC) Additional “rows” for combined analog-digital model Equivalent cost (SoC) Equivalent cost (SiP)

  28. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity – MPU Frequency Scaling Outreach

  29. Power-Constrained MPU Frequency 2007: power limit led to 8%/year MPU frequency scaling, BELOW 13%/year intrinsic device CV/I scaling 2010: 8%/year too aggressive, given markets and devices 2009 ITRS +8%/yr frequency -5%/yr switching 2011 Revision +0%/yr frequency +0%/yr switching +4%/yr frequency -5%/yr switching +0%/yr frequency -5%/yr switching

  30. Example Impact: Design-PIDS Cross-TWG Device speed “headroom” enables power savings in Design What selection of devices can PIDS provide together in a process? High Performance (HP): Highest Ion and Ioff, lowest CV/I Low Operating Power (LOP): Lowest VDD, medium Ion, Ioff and CV/I Low Standby Power (LSTP): Lowest leakage, low Ion, high CV/I What ratio of device characteristics does Design want? Preferred order of dynamic power: LOP < LSTP << HP Preferred order of leakage power: LSTP < LOP << HP Design PIDS Application- and Market-driven Technology-driven

  31. Today’s Agenda 2010 Updates: Design Cost, SOC System Driver 2011 Design Power Roadmap 2011 Verification Roadmap 2011 MTM: SOC vs. SIP (RF/AMS Sub-Driver) Cross-TWG Activity Outreach

  32. Gaps in EDA (IEEE DAC Roadmap Workshop 2010) Technology EDA nature Metrics 32

  33. THE ITRS ROADMAP Markets Applications Systems Products MTM ERD, ERM, ERA RF/AMS M&S Test ESH FI A&P YE PIDS Interconnect FEP Litho Metrology ORTCs

  34. Design and System Drivers Europe: Ralf Brederlow, Wolfgang Ecker, Eric Flamand, Frederic Lalanne, Alfonso Maurelli, Wolfgang Rosenstiel, Jean-Pierre Schoellkopf, Peter Van Staa, Maarten Vertregt Japan: Yoshimi Asada, Kenji Asai, Tamotsu Hiwatashi, Koichiro Ishibashi, Masaru Kakimoto, Haruhisa Kashiwagi, Masami Matsuzaki, Kazuya Morii, Mamoru Mukuno, Katsutoshi Nakayama, Nobuto Ono, Toshitada Saito, Hiroshi Shibuya, Mikio Sumitani, Hiroki Tomoshige, Tadao Toyoda, Ichiro Yamamoto Korea: Chanseok Hwang, Chang Kim, Min Hwahn Kim USA: Fawzi Behmann, Valeria Bertacco, Yu Cao, Juan-Antonio Carballo, John Darringer, Dale Edwards, Praveen Elakkumanan, Kwangok Jeong, Bill Joyner, Andrew Kahng, Vinod Kathail, Victor Kravets, Austin Lesea, Sung Kyu Lim, Vinod Malhotra, Prasad Mantri, Grant Martin, Nikil Mehta, Sani Nassif, Bernie New, David Pan, Shishpal Rawat, Kambiz Samadi, Gary Smith, Leon Stok, Alfred Wong, David Yeh Thank You!