2004 Spring Workshop Insights: Test Roadmap Updates and Interconnect Challenges
The 2004 Spring Workshop held in Stressa, Italy, brought together industry experts from Philips, Infineon, STMicroelectronics, Synopsys, and more, to discuss advancements in test methodologies and roadmaps. Key updates included minor revisions to tables, an increased focus on analog/RF requirements, and the introduction of new EDA DFT tools. The workshop also highlighted emerging challenges in assembly, packaging, factory integration, and the implications of local interconnect delays on testing methods. A collaborative approach is necessary to enhance yield management and address DFT content handling.
2004 Spring Workshop Insights: Test Roadmap Updates and Interconnect Challenges
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Presentation Transcript
ITRS Test TWG Don Edenfeld April 20th, 2004 Spring Workshop - Stressa, Italy
Attendees • Rene Segers, Philips • Robert van Rijsinge, Philips • Peter Muhmenthaler, Infineon • Davide Appello, ST Microelectronics • Tom Williams, Synopsys • Burnie West, NPTest • Don Edenfeld, Intel • Anzou-san, Toshiba, DFT SWG • Noguchi-san, NECEL, ATE SWG
Roadmap Plans • 2004 Update • Minor changes to most tables • Increased focus on analog/RF table, introduction of power device requirements • 2005 Revision • Reliability Screens • Merge of logic tables • Merge embedded memory with SOC • Addition of EDA DFT tools and DFx content • Addition of test & burn-in sockets and test interface boards
Cross-TWG Outcomes • Assembly & Packaging • New package technologies have potential impact on test, requires further evaluation • Factory Integration • Further dialog on intelligent yield management systems to support increases use of adaptive test • Design • Further discussion required to close on handling of DFT content of the roadmap – what & where • Interconnect • Increasing delay on local interconnect will have a dramatic impact on test methods – requires further evaluation • Yield Enhancement • Not on Spring schedule, but need dialog
