ITRS Conference FEP- TWG Report July 16, 2003

1. ITRS ConferenceFEP- TWG ReportJuly 16, 2003

2. Starting Materials: H. Huff, D. Meyers Surface Preparation: Jeff Butterbaugh, D. Riley Thermal Films: C. Osburn, H. Huff FEOL Etch: Y. Kim, G. Smith Doping: L. Larson, D. Mercer DRAM Trench Capacitor: Europe FEP, B. Vollmer DRAM Stack Capacitor: Japan FEP, Kubota-san, Kaneda-san Flash Memory: Europe FEP, M. Alessandri FeRAM: Japan FEP, Kubota-san FEP Technology Working Groups

3. Challenges surrounding the introduction of a host of new materials, required to support continued scaling High k gate dielectric layers Dual metal gates New DRAM storage capacitor structures and materials New substrate materials such as SOI and strained silicon Alternate memory devices and materials, e.g. MRAM, FeRAM The probable introduction and CMOS integration of non-standard, dual-gate MOSFET’s e.g. FINFET FEP- The Grand Challenges

4. Production Ramp of SOI substrates- Production capacity & capability Metrology capability New Substrate Materials Likely- Strained silicon on bulk Strained silicon on SOI May be a family of products Site Flatness (FEP Difficult Challenge) Difficult to achieve Wafer/chuck interactions add to overall non-flatness Wafer/Chuck interactions poorly understood Starting Materials, Near- Term Issues & Challenges

5. Next-Generation Starting Material Cost-effective scaling of current manufacturing processes may not be viable Will probably have 2x area of 300mm wafer Will probably not be bulk silicon SOI? R& D Gap Research must start 8 years prior to substrate production ramp (predicates 2005 start) Financial conditions in Wafer Supplier industry precludes timely start of R&D Starting Materials, Long-term Issues & Challenges

6. Near-tem red wall FEP surface cleaning with zero silicon loss FEP surface cleaning with zero silicon oxide loss Cleaning process for newly introduced materials High-k gate dielectric material(s) DRAM High-k capacitor dielectric materials EPI Silicon:Germanium Strained silicon Cleaning of high aspect ratio structures Stacked and Trench capacitors Vias Fragile structures limit cleaning options FEP Surface Preparation

7. FEP Surface-Preparation, Near-Term Red Wall Note: Loss is defined as the average lost per pass, experienced after multiple cleaning passes: e.g. 0.2 Angstrom loss/pass is equivalent to 2 Angstrom loss after 10 cleaning passes For Mask-removal Dry strip and clean processes the above requirements reflect the maximum allowed substrate loss after the combined strip & clean process.

8. Gate Etch Variance allocation between lithography and etch changed (recognizes that Litho has a larger number of variance contributions) New variance (2) allocation: 4/5 Lithography, 1/5 etch Etch processes and Lithography processes assumed to be statistically independent ( tables do not account for added potential variance terms associated with litho/etch interactions) Overall Variance of Litho and etch processes  10% Lg Near term red-walls for both Lithography and etch, Etch red wall result from process capability as well as metrology capabilities Work-arounds are assumed to exist Live with less than optimum yield or device performance System design to accept greater gate length variance STI etch to be added to 2003 Roadmap Front-End Etch

9. Etch Challenges Work-arounds exist

10. Most challenging issue remains the introduction of High-k gate dielectric layers Candidate materials are emerging but none are free of major disadvantages Interface states at channel and at polysilicon gate electrode Poor charge carrier mobility Threshold voltage shifts CMOS integration challenges High-k gate dielectric layers require introduction before 2007 for all high performance and low standby power MOSFETS Lowered gate leakage allowance (vs 2001 ITRS) for HP drives need High-k gate dielectric in 2007 Gate leakage for Low Standby Power Devices drives need for high-k gate dielectric in 2006 Gate Dielectric Layer Thickness control is emerging as an important challenge STI added for 2003 Roadmap FEP Thermal/Films

11. Thermal/Films Red Walls

12. STI Thermal Films Requirements

13. Major challenges continue to surround the achievement of ultra-shallow, abrupt, highly activated drain extensions. Drives innovation in ion implantation processes & equipments Drives R&D for very rapid activation processes Attempts at more sophisticated model-based forecasting of Source/Drain requirements have not yet yielded conclusive results S/D requirements highly interactive with overall transistor design S/D requirements for bulk devices are different from SOI and future non-planar double gate devices Modeling of polysilicon gate depletion suggest that metal gates have potential to significantly extend the life of SiON gate dielectric materials FEP/Doping

14. Doping Challenges Accurate forecasting of parasitic resistance requirements essentially requires the optimized design for the MOSFET at each technology node- not a feasible task for the doping TWG TWG is searching for suitable process that will result in “reasonable” forecasted requirements for future devices

15. HP Logic, Metal Gate Delays Need for High-k Gate Dielectric Modeling done by H. Gossmann, Axcelis Technologies Inc.

16. DRAM 90nm ½ Pitch brought in from 2004 to 2003 Discussions still on-going regarding this issue Chip Size Model modified, based on survey of DRAM manufacturers Storage cell area increased from prior ITRS DRAM peripheral area decreased from prior ITRS Need for very high-k storage capacitor dielectric materials (e.g. BST) delayed beyond 2009 Aluminum Oxide, Aluminates (e.g. HfAlOx) and Tantalum oxide remain capacitor materials of consideration for the 2003-9 time period Capacitor structure migrates from MIS to MIM in order to avoid challenges regarding capacitor dielectric thickness Total interlevel metal +dielectric (except storage node) is assumed to be 1.08nm at the 180nm node, and to decrease at a rate of 10% every three years. Storage node heights, dielectric constants of high-k materials, and capacitor structures (cylinder, etc) remain unchanged from prior roadmaps DRAM Stacked Capacitor

17. DRAM Stacked Capacitor Requirements

18. No major table update Definition of technology node and text modifications, to be submitted for approval Flash Memories

19. contact contact active & poly1 active & poly1 poly2 poly2 Metal1 Metal1 top view of 2 memory cells Metal 1 contact cross section along the word line poly2 poly1 active area half pitch cell pitch Flash memorytechnology nodedefinition The technology node for both NAND and NOR Flash is defined considering the half pitch of the memory cell in the word line (poly 2) direction