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ARM Instructions I

ARM Instructions I. Prof. Taeweon Suh Computer Science Education Korea University. Data Processing Instructions. Arithmetic instructions Logical instructions Comparison instructions Move instructions. Execution Unit in ARM. Data processing instructions take 2 source operands:

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ARM Instructions I

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  1. ARM Instructions I Prof. Taeweon Suh Computer Science Education Korea University

  2. Data Processing Instructions • Arithmetic instructions • Logical instructions • Comparison instructions • Move instructions

  3. Execution Unit in ARM • Data processing instructions take 2 source operands: • One is always a register. • The other is called a shifter operand (either immediate or a register). If the second operand is a register, it can have a shift applied to it. Rn (1st source) Rm Barrel Shifter No pre-processing Pre-processing N (=shifter_operand) (2nd source) ALU Rd Source: ARM Architecture Reference Manual

  4. Arithmetic Instructions Rn Rm Syntax: <instruction>{cond}{S} Rd, Rn, N Barrel Shifter N ALU Rd

  5. ARM Arithmetic Instructions • ARM Arithmetic instructions include add, adc, sub, sbcand some more • Check out the Architecture Reference Manual for the list of all arithmetic instructions ARM assembly code # R0 = a, R1 = b, R2 = c add R0, R1, R2 High-level code a = b + c compile

  6. Arithmetic Instructions – ADD • ADD adds two operands, placing the result in Rd • Use S suffix to update conditional field • The addition may be performed on signed or unsigned numbers ADD R0, R1, R2 ; R0 = R1 + R2 ADD R0, R1, #256 ; R0 = R1 + 256 ADDS R0, R2, R3,LSL#1 ; R0 = R2 + (R3 << 1) and update flags

  7. add add r1, r2, r3 # r1 <= r2 + r3 0 0001 0011 0 0010 1110 00000000 ARM architect defines the opcode 1000 0010 0001 0011 0000 0000 binary 1110 0000 hexadecimal 0xe082 1003

  8. Immediate • 8-bit immediate field in ARM instructions limits values to the range of (0 ~ 255 (28–1)) • They are called immediates because they are immediately available from the instructions • They do not require a register or memory access

  9. add add r4, r5, #255 # r4 <= r5 + 255 0 1111 1111 0100 1 0101 1110 0000 ARM architect defines the opcode 1000 0101 0100 1111 1111 0000 binary 1110 0010 hexadecimal 0xe285 40ff

  10. Rm with Barrel Shifter Encoded here add r0, r1, r2, LSL #1 add r0, r1, r2, LSL r3 LSL: Logical Shift Left LSR: Logical Shift Right ASR: Arithmetic Shift Right ROR: Rotate Right RRX: Rotate Right with Extend

  11. Arithmetic Instructions – SUB • SUB subtracts operand 2 from operand 1, placing the result in Rd • Use S suffix to update conditional field • The subtraction may be performed on signed or unsigned numbers SUB R0, R1, R2 ; R0 = R1 - R2 SUB R0, R1, #256 ; R0 = R1 - 256 SUBS R0, R2, R3,LSL#1 ; R0 = R2 - (R3 << 1) and update flags

  12. sub sub r4, r5, #255 # r4 <= r5 - 255 ARM architect defines the opcode 1 1110 0 0101 0100 0000 1111 1111 ARM architect defines the opcode 0100 0101 0100 1111 1111 0000 binary 1110 0010 hexadecimal 0xe245 40ff

  13. Examples Before: Before: r0 = 0x0000_0000 r1 = 0x0000_0005 ADD r0, r1, r1, LSL#1 r0 = 0x0000_0000 r1 = 0x0000_0002 r2 = 0x0000_0001 SUB r0, r1, r2 After: After: r0 = 0x0000_0001 r1 = 0x0000_0002 r2 = 0x0000_0001 r0 = 0x0000_000F r1 = 0x0000_0005

  14. Examples • Why is the C flag set (C = 1)? cpsr = nzcv r1 = 0x0000_0001 SUBS r1, r1, #1 Before: cpsr = nZCv r1 = 0x0000_0000 After:

  15. Logical Instructions Rn Rm Syntax: <instruction>{cond}{S} Rd, Rn, N Barrel Shifter N ALU Rd

  16. ARM Logical Instructions • ARM logical instructions include and, orr, eor, bic • Logical instructions operate bit-by-bit on 2 source operands and write the result to the destination register compile ARM assembly code # R0 = a, R1 = b, R2 = c and R0, R1, R2 High-level code a = b & c ;

  17. Logical Instructions – AND • AND performs a logical AND between the two operands, placing the result in Rd • It is useful for masking the bits AND R0, R0, #3 ; Keep bits zero and one of R0 and discard the rest

  18. Logical Instructions – EOR • EOR performs a logical Exclusive OR between the two operands, placing the result in the destination register • It is useful for inverting certain bits EOR R0, R0, #3 ; Invert bits zero and one of R0

  19. Examples r1 = 0b1111 r2 = 0b0101 BIC r0, r1, r2 r0 = 0x0000_0000 r1 = 0x0204_0608 r2 = 0x1030_5070 ORR r0, r1, r2 Before: Before: r0 = 0x1234_5678 r0 = 0b1010 After: After:

  20. AND, OR, and EOR Usages • and, or, nor • andis useful for masking bits • Example: mask all but the least significant byte of a value: 0xF234012F AND 0x000000FF = 0x0000002F • or is useful for combining bit fields • Example: combine 0xF2340000 with 0x000012BC: 0xF2340000 OR 0x000012BC = 0xF23412BC • eoris useful for inverting certain bits: • Example: A EOR 3

  21. Comparison Instructions • The comparison instructions update the cpsr flags according to the result, but do not affect other registers • After the bits have been set, the information can be used to change program flow by using conditional execution Rn Rm Barrel Shifter N Syntax: <instruction>{cond}{S} Rn, N ALU Rd

  22. Comparison Instructions – CMP • CMP compares two values by subtracting the second operand from the first operand • Note that there is no destination register • It only update cpsr flags based on the execution result CMP R0, R1;

  23. Move Instructions Rn Rm Barrel Shifter Syntax: <instruction>{cond}{S} Rd, N N ALU Rd

  24. Move Instructions – MOV • MOV loads a value into the destination register (Rd) from another register, a shifted register, or an immediate value • Useful to setting initial values and transferring data between registers • It updates the carry flag (C), negative flag (N), and zero flag (Z) if S bit is set • C is set from the result of the barrel shifter MOV R0, R0; move R0 to R0, Thus, no effect MOV R0, R0, LSL#3 ; R0 = R0 * 8 MOV PC, R14; (R14: link register) Used to return to caller MOVS PC, R14; PC <- R14 (lr), CPSR <- SPSR ; Used to return from interrupt or exception * SBZ: should be zeros

  25. MOV Example cpsr = nzcv r0 = 0x0000_0000 r1 = 0x8000_0004 MOVS r0, r1, LSL #1 Before: cpsr = nzCv r0 = 0x0000_0008 r1 = 0x8000_0004 After:

  26. Branch Instructions • A branch instruction changes the flow of execution or is used to call a function • This type of instructions allows programs to have subroutines, if-then-else structures, and loops Syntax: B{cond} label BL{cond} label

  27. B, BL • B (branch) and BL (branch with link) are used for conditional or unconditional branch • BL is used for the subroutine (procedure, function) call • To return from a subroutine, use • MOV PC, R14; (R14: link register) Used to return to caller • Branch target address • Sign-extend the 24-bit signed immediate (2’s complement) to 30-bits • Left-shift the result by 2 bits • Add it to the current PC (actually, PC+8) • Thus, the branch target could be ±32MB away from the current instruction

  28. Examples B forward ADD r1, r2, #4 ADD r0, r6, #2 ADD r3, r7, #4 forward: SUB r1, r2, #4 BL my_subroutine CMP r1, #5 MOVEQ r1, #0 ….. My_subroutine: < subroutine code > MOV pc, lr // return from subroutine backward: ADD r1, r2, #4 SUB r1, r2, #4 ADD r4, r6, r7 B backward

  29. Memory Access Instructions • Load-Store (memory access) instructions transfer data between memory and CPU registers • Single-register transfer • Multiple-register transfer • Swap instruction

  30. Single-Register Transfer

  31. LDR (Load Register) • LDR loads a word from a memory location to a register • The memory location is specified in a very flexible manner with addressing mode // Assume R1 = 0x0000_2000 LDR R0, [R1] // R0 ← [R1] LDR R0, [R1, #16] // R0 ← [R1+16]; 0x0000_2010

  32. STR (Store Register) • STR stores a word from a register to a memory location • The memory location is specified in a very flexible manner with a addressing mode // Assume R1 = 0x0000_2000 STR R0, [R1] // [R1] <- R0 STR R0, [R1, #16] // [R1+16] <- R0

  33. CPU Execution Example (ARM) ARM CPU PC (r15) Address Bus 0x0000 0x0008 0x0008 0x0004 0x0004 0x0000 Register File 32 bits Memory r0 0x00110011 0x00220022 0x00220022 0x00110011 0x0018 0x0014 0x0008 0x0004 0x0000 0x0018 0x0014 r1 0x00110011 Data Bus 0x00220022 r2 + R3 r3 0x00330033 add r2, r2, r3 ldr r3, [r13, 8] ldr r2, [r13, 4] add r2, r2, r3 … ldr r3, [r13, 8] ldr r2, [r13, 4] r13 r14 Assume that r13 contains 0x0010

  34. Load-Store Addressing Mode ! Indicates that the instruction writes the calculated address back to the base address register After: r0 ← mem[0x0009_0004] r0 = 0x0202_0202 r1 = 0x0009_0004 LDR r0, [r1, #4]! Before: r0 = 0x0000_0000 r1 = 0x0009_0000 Mem32[0x0009_0000] = 0x01010101 Mem32[0x0009_0004] = 0x02020202 After: r0 ← mem[0x0009_0004] r0 = 0x0202_0202 r1 = 0x0009_0000 LDR r0, [r1, #4] After: r0 ← mem[0x0009_0000] r0 = 0x0101_0101 r1 = 0x0009_0004 LDR r0, [r1], #4

  35. (Assembly) Language • There is no golden way to learn language • You got to use and practice to get used to it

  36. Backup Slides

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