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## CMOS Digital Integrated Circuits

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**CMOS Digital Integrated Circuits**Lec 12 Dynamic Logic Circuits**Dynamic Logic Circuits**• Goals Understand • Pass transistors circuits • Voltage bootstrapping • Synchronous dynamic circuit techniques • Dynamic CMOS circuit techniques • High-performance dynamic CMOS circuits**Static v.s. Dynamic**• Static Logic Gates • Valid logic levels are steady-state operating points • Outputs are generated in response to input voltage levels after a certain time delay, and it can preserve its output levels as long as there is power. • All gate output nodes have a conducting path to VDD or GND, except when input changes are occurring. • Dynamic Logic Gates • The operation depends on temporary storage of charge in parasitic node capacitances. • The stored charge does not remain indefinitely, so must be updatedor refreshed. This requires establishment of an update or recharge path to the capacitance frequently enough to preserve valid voltage levels.**Static v.s. Dynamic (Continued)**• Advantages of Dynamic Logic Gates • Allow implementation of simple sequential circuits with memory functions. • Use of common clock signals throughout the system enables the synchronization of various circuit blocks. • Implementation of complex circuits requires a smaller silicon area than static circuits. • Often consumes less dynamic power than static designs, due to smaller parasitic capacitances.**Pass-Transistor LatchCircuit and Operation**• Operation • CK = H, D=H or L: CX is charged up or down through MP, and X becomes H or L (depends on D input) since MP is on D and X are connected. • CK = L: X is unchanged since MP is off and CX is isolated from D, and the charge is stored on capacitances CX. • For X = H, Q = L and Q = H • For X = L, Q = H and Q = L • Cost: 3 to 5 devices (very low) Soft note ML Q Vx Q D MP X MD Cx CK**Pass-Transistor LatchSoft Node Concept**• During CK = 1: Let D = 1, i.e. VD = VOH = VDDMP is conducting and charges CX to a “weak 1” (VX = VDD – VTD) Q = L (VQ<VTD) and Q = H(VQ=VDD). • During CK = 0: Logic-level VX is preserved through charge storage on CX. However, VX starts to drop due to leakage. • What value does VX have to deteriorate to no longer like a stored ? Example (see p359~359, Kang and Leblebici): For an inverter with VDD = 5V, VT,n = 0.8V , VOL = 2.9V and VIH = 2.9V, initial VX =4.2 V. But due to leakage currents, this will decline over time. When it declines below VIH(2.9V), then a logic 0 out of the inverter can no longer guaranteed. Thus, to avoid an erroneous output, the charge stored in CX must be restored or refreshed to its original level before VX declines below 2.9 V.**Soft note**ID Vx Vx Vin=VDD D S Vin MP X X MP Cx Cx CK CK Basic Principles of Pass Transistor CircuitsLogic “1” Transfer • Logic “1” Transfer:VX(t=0)=0V, Vin=VOH=VDD, CK=0VDD • VGS = VDD - VX, VDS = VDD - VX = VGS. • Therefore, VDS> VGS – VT,MP MP is in saturation. • Note that the VT,MP is subject to substrate bias effect and therefore, depends on the voltage level VX. We will neglect the substrate bias effect for simplicity.**Basic Principles of Pass Transistor CircuitsLogic “1”**Transfer (Cont.) • Integrating the above equation with t from 0 t and VX from 0 VX, we have • Therefore, • and,**VX**Vmax=VDD-VT,MP Vmax t 0 Basic Principles of Pass Transistor CircuitsLogic “1” Transfer (Cont.) • VX rises from 0V and approaches a limit value Vmax = VX(t)|t= = VDD-VT,MP, but it can not exceed this value, since the pass transistor will turn off at this point (VGS=VT,MP). Therefore, it transfers a “weak logic 1”. • The actual Vmax by taking the body effect into account is, • and tcharge = time to VX = 0.9Vmax, • Body Effect: Reduce VX, and Increase tcharge**Soft note**ID Vx Vx Vin=0 S D Vin MP X X MP Cx Cx CK CK Basic Principles of Pass Transistor CircuitsLogic “0” Transfer • Logic “0” Transfer:VX(t=0)=Vmax= VDD – VT,MP, Vin=VOL=0V, CK= 0 VDD • VGS = VDD, VDS = Vmax = VDD – VT,MP. • Therefore, VDSVGS – VT,MP MP is in linear region. • Note that the VSB=0. Hence, there is no body effect for MP (VT,MP= VT0,MP). But the initial condition VX(t=0)=VDD – VT,MP contains the threshold voltage with body effect. To simplify the expressions, we will use VT,MP in the following.**Basic Principles of Pass Transistor Circuits Logic “0”**Transfer (Cont.) • Integrating the above equation with t from 0 t and VX from VT,MPVX, we have • Therefore, • and,**VX**Vmax=VDD-VT,MP Vmax t 0 Basic Principles of Pass Transistor Circuits Logic “0” Transfer (Cont.) • VX drops from Vmax= VDD-VT,MP, to 0V. Hence, unlike the charge-up case, it transfers a “strong logic 0”. • fall = time of VX drops from 0.9Vmax to 0.1Vmax, • where,**Ileakage**Igate=0 Vx Vin =0 MP Cx CK=0 VCK=0 Ileakage VX Vin=0 CX Isubthreshold n+ n+ Ireverse p-type Si Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage • At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX will gradually leak away, primarily due to the leakage currents associated with the pass transistor. The gate current of the inverter driver transistor is negligible.**Basic Principles of Pass Transistor Circuits Charge Storage**and Charge Leakage (Cont.) VCK=0 Ileakage VX • Isubthreshold is thesubthreshold current for the pass transistor with CK=0. • Ireverse is the reverse current for the source/drain pn junction at node X • Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX • Cin: due to oxide-related parasitics, can be considered constants. Vin=0 CX n+ n+ Isubthreshold Ireverse p-type Si Ileakage= Isubthreshold + Ireverse Ileakage Vx Cin= Cgb+ Cpoly+ Cmetal Cj(VX) Cin Isubthreshold Ireverse CX= Cin + Cj Drain-substrate pn-junction**Ileakage= Isubthreshold + Ireverse**Ileakage Vx Cin= Cgb+ Cpoly+ Cmetal Cj Cin Isubthreshold Ireverse CX= Cin + Cj Drain-substrate pn-junction Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.) • The total charge stored in the soft node can be expressed as, Q = Qj(VX) + Qin where Qin = Cin•VX • The total leakage current can be expressed as the time derivative of the total soft-node charge Q**Basic Principles of Pass Transistor Circuits Charge Storage**and Charge Leakage (Cont.) • Where • Therefore, • We have to solve the above differential equation to estimate the actual charge leakage time from the soft node.**Basic Principles of Pass Transistor Circuits Charge Storage**and Charge Leakage (Cont.) • A quick estimate of the worst-case leakage behavior • Assume that the minimum combined soft-node capacitance is CX,min = Cgb + Cpoly + Cmental + Cdb,min Cdb,min is the minimum junction capacitance, obtained when VX=Vmax • The worst-case holding time(thold) is the shortest time for VXto drop from its initial logic-high value to the logic threshold voltage due to leakage. thold =Qcritical,min/Ileakage,max • where Qcritical,min =CX,min (Vmax-VDD/2) Vth**Vx**MP M1 Cx CK soft node 3 6 6 5 1 2 2 4 5 MP M1 2 1 1 4 3 CK diffusion metal polysilicon Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.) • Example 9.2:Consider the soft-node structure shown below, which consists of the drain (or source, depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of an nMOS driver transistor via a metal interconnect. Question: is to estimate thold if VDD=5V and the soft-node is initially charged to Vmax.**3**6 6 5 1 2 2 4 5 MP M1 2 1 1 4 diffusion metal polysilicon 3 CK Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont.) • Material parameters: VTO = 0.8V COX = 0.065 fF/m2 = 0.4V1/2 C’metal = 0.036 fF/ m2 |2F| = 0.6V C’poly = 0.055 fF/ m2 0 = 0.88V Cj0 = 0.095 fF/ m2 0SW = 0.95V Cj0SW = 0.2 fF/m Ileakage,max = 0.85 pA Soft-node Capacitance Calculation • Oxide-related (constant) parasitic capacitances • Cgb=COX·W·Lmask=0.065 fF/m2·(4 m2 m) =0.52 fF • Cmetal=C’metal·W·Lmetal=0.036 fF/m2·(5 m5 m) =0.90 fF • Cploy=C’poly·W·Lpoly=0.055 fF/m2·(36+6+2 m2) =2.42 fF**Basic Principles of Pass Transistor Circuits Charge Storage**and Charge Leakage (Cont.) • Parasitic junction capacitance By zero-bias unit capacitance values in the previous slide, we have • Cbottom=Abottom·Cj0=0.095 fF/m2·(36 m2+ 12 m2 ) =4.56 fF • Csidewall=Cj0SW·Psidewall=0.2 fF/m2·(30 m) =6.00 fF Therefore • Cdb,max=Cbottom + Csidewall=4.56 fF + 6.00 fF=10.56 fF The minimum drain junction capacitance is achieved as the junction is biased with Vmax. We need to find Vmax to determine Cdb,min • Vmax = 5.0 - 8.0 - 0.4 ( 0.6+ Vmax - 0.6 ) Vmax = 3.68 V Therefore,**Basic Principles of Pass Transistor Circuits Charge Storage**and Charge Leakage (Cont.) • Combining the Oxide-related (constant) parasitic capacitances with the parasitic junction capacitance, CX,min can be got as CX,min = Cgb + Cpoly + Cmental + Cdb,min = 0.52 + 2.42 + 0.90 +4.71 = 8.55 fF • The amount of the critical charge drop is Qcritical = CX,min(VX,min-VDD/2)=8.55 (3.68-2.5)=10.09 fC • Finally, thold= Qcritical /Ileakage,max=11.87ms • The worst-case hold time for this structure is relatively long, even with a very small soft-node capacitance of 8.55fF. It means that the logic gate can be preserved in a soft node for a long time period when the leakage current is small.**VDD**M2 Vx Vout Vin M1 Cout Voltage Bootstrapping • The Voltage bootstrapping is a technique to overcome the threshold voltage drops of the output voltage levels in pass transistor gates or enhancement-load inverters and logic gates. • Consider the following circuit with VXVDD M2 is in saturation. If Vin is low, the maximum output voltage is limited as Vout(max) = VX – VT2(Vout)**VDD**M3 Vx M2 CS Cboot Vout Vin M1 Cout Voltage Bootstrapping (Cont.) • To overcome the voltage drop, the voltage VX must be increased. This can be achieved by adding a third transistor M3 into the circuit. • CS and Cboot represent the capacitances which dynamically couple VX to the ground and to the output. • The goal of the above circuit is to provide a high enough voltage VX to let Vout go to VDD instead of VDD-VT2(Vout). • Initially, let Vin=H M1 and M2are on, and Vout=L. • Now Vin goes to L M1 turns off, and Vout starts to rise. This change will be coupled to VX through the bootstrap capacitor, Cboot.**Voltage Bootstrapping (Cont.)**• Let iCboot be the transient current through Cboot during the charge-up event, and let iCS be the current through CS. Assume iCSiCboot, we have iCSiCboot CS·dVX/dt Cboot·d(Vout-VX)/dt (CS+Cboot)·dVX/dt Cboot·dVout/dt dVX/dt Cboot /(CS+Cboot) ·dVout/dt • This expression can be integrated to give VX such that Vout will rise to VDD. • If Cboot >> CS, then for Vout rising to VDD, VX(max) 2VDD – VT3 – VOL > VDD – VT2. for realistic values of the voltages. Thus, it is feasible to use the circuit to obtain Vout =VDD.**Voltage Bootstrapping (Cont.)**• To overcome the threshold voltage drop at Vout, the minimum VX is VX(min) = VDD + VT2|Vout = VDD = [VDD-VT3(VX)]+Cboot/(CS+Cboot) ·(VDD-VOL) • Therefore, the required capacitance ratio Cboot /(CS+Cboot) is • CS is the sum of the parasitic source-to-substrate capacitance of M3 and the gate-to-substrate capacitance of M2.**VDD**M3 Vx M2 Cboot Vout Vin M1 Voltage Bootstrapping (Cont.) • Cboot can be specifically constructed to control its value by using a transistor with the source and drain connected together at Vout and the gate attached to VX. Since its drain and source tied together, it simply acts as an MOS capacitor between VX and Vout. • See Kang and Leblebici at pp. 373 for a SPICE example.**F1**A F2 B Comb. Comb. Comb. Logic Logic Logic 2 1 C D 1 1 2 3 1 t 2 phase1 phase2 t 1,2 non-overlapping clocks Synchronous Dynamic Circuit Techniques –Dynamic Pass Transistor Circuits • The multi-stage synchronous circuit is shown below. The circuit consists of cascaded combinational logic stages interconnected through nMOS pass transistors. Its operation depends on temporary charge storage in the parasitic input capacitances. • Logic levels are stored on input capacitances during the inactive clock phase.**VDD**VDD VDD 1 2 1 Vout Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Dynamic Pass Transistor CircuitsTwo-Phase Clock Dynamic Shift Register • Depletion-Load Dynamic Shift Register • The max clock frequency is determined by signal propagation delay through one inverter stage. • One half-period of the clock signal must be long enough to allow Cin to charge up or down, and Cout to charge to the new value. • The logic-high input value is one VT0 lower than VDD.**Dynamic Pass Transistor CircuitsEnhancement-Load**DynamicShift Register • Enhancement-Load Dynamic Shift Register 1 • Instead of biasing load transistors with a constant gate voltage, a clock signal is applied to the gate of the load transistor power dissipation and silicon area are reduced. • The power supply current flows only when the load devices are activated by the clock signal, the power consumption is lower than the depletion-load nMOS logic. VDD VDD VDD 1 2 1 2 Vout Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3**VDD**VDD 2 1 1 Z A B C D nMOS nMOS Logic Logic Stage 1 Stage 2 Enhancement-Load Dynamic Shift Register1 (Cont.)General Structure General Circuit Structure of Ratioed Synchronous Dynamic Circuit**Enhancement-Load Dynamic Shift Register 1 (Cont.)**VDD VDD VDD 1=H 2 1 1 2 • VOL→ kdriver/kload Ratioed Dynamic Logic. • Cout1, Cin2 & Cout2, Cin3 interact Charge Sharing Vout1 Vout2 Vout3 Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Vout2VOL VDD VDD VDD 2=H 2 1 1 2 Vout1 Vout2 Vout3 Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Vout1VOL Vout3VOL**VDD**VDD VDD 1 2 1 Vout Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Enhancement-Load Dynamic Shift Register 2 • Enhancement-Load Dynamic Shift Register 2 • The input pass transistor and the load transistor are driven by the same clock phase. • The valid low-output voltage level VOL=0V can be achieved regardless of the driver-to-load ratio, this circuit is a ratioless dynamic logic.**VDD**VDD 1 2 Z A B C D nMOS nMOS Logic Logic Stage 1 Stage 2 Enhancement-Load Dynamic Shift Register 2(Cont.)General Structure General Circuit Structure of Ratioless Synchronous Dynamic Circuit**VDD**VDD VDD 1=H 2 1 1 Vout1 Vout2 Vout3 Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Vout3VOL Vout1VOL Vout2 0V 2=H VDD VDD VDD 1 2 1 Vout1 Vout2 Vout3 Vin Cout1 Cin2 Cin3 Cin1 Cout2 Cout3 Vout2VOL Vout10V Vout30V Enhancement-Load Dynamic Shift Register 2 (Cont.) • VOL→ 0V Ratioless Dynamic Logic. • Cini <<Couti-1 for i=2,3 Minimum Charge Sharing**2**Vb Va Cout1 Cin2 Enhancement-Load Dynamic Shift Register 2 (Cont.)Charge Sharing • 2 = 0:Qout1 = Cout1Vb and Qin2= Cin2Va • 2 = 1:Qtotal = Cout1Vb + Cin2Va and Ctotal = Cout1 + Cin2 The resulting voltage across Ctotal is VR = Qtotal / Ctotal = (Cout1Vb + Cin2Va )/ (Cout1 + Cin2) • If Vb = VDDand Va<< Vb VR Cout1VDD /(Cout1 + Cin2) VR VDD if Cin2<< Cout1 Charge Sharing**1**2 1 A B F1 Stage 1 Stage 2 C D 1 1 2 Dynamic CMOS Transmission Gate Logic • Each transmission gate is controlled by the clock signal and its complement. Therefore, the two-phase clocking need four clock signals. • As in the nMOS structures, the CMOS dynamic circuit relies on charge storage in parasitic input capacitances during the inactive clock cycles.**VDD**soft node CK VX Vin Vout CK CX Cy Dynamic CMOS Transmission Gate LogicShift Register • The basic building block of the shift register consists of a CMOS inverter, which is driven by a TG. • CK=1Vin is transferred onto the parasitic input capacitance CX. • The low on-resistance of TG results in • A smaller transfer time compared to nMOS-only switches. • No threshold voltage drop across TG**Dynamic CMOS Transmission Gate LogicShift Register (Cont.)**• The single-phase CMOS shift register is built by • Cascading identical inverter units • Driving each stage alternately with the CK and CK. • Ideally: The odd-numbered stages are on as CK=1, while the even-numbered stages are off the cascaded inverter stages are alternately isolated. • Practically: • The CK and CK are not a truly nonoverlapping signal pair, since their waveforms have finite rise and fall times. • One of the signals is generated by inverting the other the clock skew is unavoidable. • True two-phase clocking is preferred over single-phase clocking. CK CK CK V1 V2 V3 V4 CK CK CK**t**precharge precharge Vout t Dynamic CMOS Precharge-Evaluate LogicReduced Transistor Count VDD • =0 Cprecharges to VDD (output is not available during precharge) • =1 Cselectively discharges to 0 (output is only available after discharge is complete) Mp Vout C Internal capacitance nMOS inputs Logic Me evaluate**VDD** Mp Vout A1 B1 A2 B2 A3 Me Dynamic CMOS Precharge-Evaluate LogicAn Example Z is high when=0 Z=(A1 A2A3 +B1B2)**Dynamic CMOS Precharge-Evaluate**LogicAdvantages/Disadvantages • Advantages • Need only N+2 transistors to implement a N-input gate. • Low static power dissipation • No DC current paths to place constraints on device sizing • Input capacitance is same as pseudo nMOS gate. • Pull-up time is improved by active switch to VDD. • Disadvantages • The available time of output is less than 50 % of the time. • Pull-down time is degraded due to series active switch to 0. • Logic output value can be degraded due to charge sharing with other gate capacitances connected to the output. • Minimum clock rate determined by leakage on C. • Maximum clock rate determined by circuit delays. • Input can only change during the precharge phase. Inputs must be stable during evaluation; otherwise an incorrect value on an input could erroneously discharge the output node. (single phase P-E logic gates can not be cascaded) • Outputs must be stored during precharge, if they are required during the next evaluate phase.**Dynamic CMOS Precharge-Evaluate LogicCascading Problem**VDD VDD • Evaluate: • Me1, Me2 ON • Mp1, Me2 OFF • Problem: All stages must evaluate simultaneously one clock does not permit pipelining of stages. Mp1 precharge evaluate Mp2 Vout2 Vout1 t 1st stage 2nd Vout1 does not switch from Vout nMOS inputs “1” to “0” fast enough 1 Logic t correct state Vout Me2 erroneousstate Me1 t**precharge**evaluate 1 t High Performance Dynamic CMOS CircuitsDomino CMOS Logic Static inverter serves to buffer the logic part of the circuit from its output load VDD VDD X Vout nMOS inputs Logic • =0 • X precharges to VDD, and Vout= 0. • =1 • X remains high, and Vout remains low. • X discharges to 0, and Vout changes from 0 to 1.**VDD**VDD VDD X1 X2 X3 nMOS nMOS nMOS inputs Logic Logic Logic Domino CMOS Logic evaluate evaluate precharge teval t X1 t Max number gates limited: total propagation delay <teval X2 t X3 t**VDD**VDD VDD X3 X1 X2 nMOS nMOS nMOS inputs Logic Logic Logic Domino CMOS Logic (Cont.) • The problem in cascading conventional dynamic CMOS occurs when one or more inputs make a 1 to 0 transition during evaluation. • Domino circuits can fix the above problem • During the evaluation, each buffer output can make at most one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make at most one (0 to 1) transition.**Domino CMOS Logic The Limitations**• The static CMOS and domino gates can be used together, see Fig. 9.31. in Kang and Leblebici. The limitation:the number of inverting static logic stages in cascade must beeven, to let the inputs of next domino stage can have only 0 to 1 transitions during the evaluation. • Can implementonlynon-inverting logic • Due to precharge use, can suffer from charge sharing during the evaluation which may cause erroneous outputs. • The problem will be described in the next slide, and several solutions will be presented later.**VDD**VDD VX Vout C1 N C2 VX = VDDC1/(C1+C2) Keep C2 << C1 Domino CMOS LogicCharge Sharing • Assume that all inputs are low initially, and the voltage across C2=0V • During the precharge, C1 is charged to VDD • If transistor N switches from 0 to 1 during the evaluation phase, the charge initially stored in C1 will be shared by C2. Therefore, the value of VX will reduced.**Domino CMOS LogicReduce Charge Sharing Degradation of VX**VDD weak pull-up pMOS VX Vout nMOS inputs Logic Push VX to VDD unless there is a strong pull-down path between Vout and ground****VX1 Vout1 nMOS C1 Logic VX2 Vout2 C2 nMOS Logic Domino CMOS Logic Reduce Charge Sharing Degradation of VX (Cont.) VDD • Use separate pMOS transistors to precharge all intermediate nodes in nMOS pull-down tree which have a large parasitic capacitance. • Effectively eliminate all charge sharing problems during evaluation • Allow implementation of multiple-output domino structures. • Can cause additional delay since the nMOS tree need to drain a larger charge to pull down VX Another Way: Use a smaller threshold voltage the final stage output is not affected by lowering of VX trade off the pull-up speed (weaker pMOS transistor)**VDD**VDD VDD VX1 Vout C1 VA VX2 C2 VB Domino CMOS Logic An Example of Using Separate pMOS Transistor • Let C1= C2=0.05pF. VX1=0, and VX2=0 at t=0 • Without this extra pMOS transistor • Precharge: VX1≠VX2 • Evaluation: VX1=VDDC1/(C1+C2) = VDD/2 • With this extrapMOS transistor • Presharge:VX1 = VX2 • Evaluation:VX1= VDD • See pp.392~393 for the HSPICE simulation result • Note that there is a speed penalty for adding this extra pMOS precharge transistor.