ENG241 Digital Design

1. ENG241 Digital Design Week #9 Register Transfer and Data Paths

2. Week #9 Topics • Data Paths and Operations • The Arithmetic/Logic Unit • Register Transfer Operations • Micro-Operations • Multiplexer-Based Transfer • Bus-Based Transfer • Complete Data Path Design • Pipelining ENG241/Digital Design

3. Resources • Chapter #7, Mano Sections • 7.2 Register Transfers • 7.3 Register Transfer Operations • 7.4 VHDL and RTL • 7.5 Micro Operations • 7.6 Multiplexer Based Transfers • 7.8 Bus Based Transfers ENG241/Digital Design

4. Parts of CPUs • Datapath • Registers, Multiplexors, Adders, Subtractors and logic to perform operations on them (Comb Logic) • Control unit • Generates signals to control data-path • Accepts status signals to perform sequencing Control Data Path ENG241/Digital Design

5. Memory and I/O • Control Unit + Data Path + Memory + Input Output = Micro-computer System MEMORY Input and Output ENG241/Digital Design

6. Arithmetic/Logic Unit (ALU) • The ALU is a combinational circuit that performs a set of basic arithmetic and logic operations. • An adder can perform addition, subtraction, … • Select lines are used to determine the operation to be performed. ENG241/Digital Design

7. ALU Design using Hierarchy • This ALU has: • 2 control lines S0,S1 for arithmetic • S2 selects logical ops • Start designing in parts ENG241/Digital Design

8. One Stage ALU • Design a 1-bit Arithmetic unit • Design a 1-bit Logic unit • Combine the two units to form a 1-bit Arithmetic/Logic • Replicate as many times to form an n-bit ALU

9. Arithmetic Circuit • The basic component of an arithmetic circuit is a: • N-bit Ripple Carry Adder (Parallel Adder). • By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations (Cin is also an input) • Select lines S0, S1 can be used to control input Y. Why? ENG241/Digital Design

10. Looking Inside • Table  Functionality. • How to design the B Input Logic? • What possible functionality can I achieve if I control the ‘Y’ Value to the n-bit Adder? B Input Logic ENG241/Digital Design

11. Design of B Select Logic • Use an 8-to-1 Mux (Straight forward Solution). • Or … use a 4-to-1 mux! • Can we do better? • YES: simplify the expression from the truth table using a K-Map ENG241/Digital Design

12. 1-bit (Single Stage) Arithmetic Circuit • The B logic is nothing but a 2-to-1 Mux instead of the 4-to-1 Mux ENG241/Digital Design

13. 4-Bit Circuit • Duplicating the one stage four times will produce a 4-bit circuit ENG241/Digital Design

14. Logic Section Design • Generous number of operations ENG241/Digital Design

15. Arithmetic/Logic Unit • The logic circuit can be combined with the arithmetic circuit to produce an ALU. • Selection variables S1 and S0can be common to both circuits, • A third selection variable S2 can be used to differentiate between the logic and arithmetic operations. ENG241/Digital Design

16. One Stage Arithmetic Circuit ENG241/Digital Design

17. One Stage Logic Circuit ENG241/Digital Design

18. One Stage ALU • Mux to choose Arithmetic or Logic ENG241/Digital Design

19. n-bit ALU • Duplicate the one stage n times!! ENG241/Digital Design

20. Resulting Control • The one stage ALU can provide 8 arithmetic and four logic operations. ENG241/Digital Design

21. Register Transfer Language (RTL) • Register Transfer Language (RTL): used to describe CPU organization in high-level terms • RTL expressions are made up of elements which describe the registers being manipulated, and the micro-ops being performed on them • Here are the basic components of RTL expressions:

22. Register Transfer Language (RTL) • Registers named in uppercase • PC, IR (instruction), R3 • The operations on the data in registers are called microoperations ENG241/Digital Design

23. Micro-Operations • Basic operations of the datapath • Example: • Moving data from one register to another • Adding the contents of two registers • Incrementing the contents of a register • The control unit provides the signals that sequence the micro-operations in a prescribed manner • The results of a currently executing micro-operation may determine both the sequence of control signals and the sequence of future micro-operations to be executed (e.g. BNE) • A micro operation is expected to complete in one clock ENG241/Digital Design

24. RTL • Transfer from R1 to R2 • R2  R1 • R2 is destination • R1 is source • Conditional • If(K1 = 1) then (R2  R1) • K1: R2 R1 as a shorter form ENG241/Digital Design

25. Transfer • K1: R2 R1 • Transfer at the clock edge • When K1 is high • n bits wide ENG241/Digital Design

26. Symbols • Note memory transfers • DR  M[AR] (contents of Memory) ENG241/Digital Design

27. Syntax not VHDL (similar) ENG241/Digital Design

28. Types of Microoperations • Transfer – (have just looked at) • Arithmetic • Logic • Shift ENG241/Digital Design

29. Arithmetic • Basic ops (addition, subtraction, ..) • R0  R1 + R2 • Subtraction by 2’s complement ENG241/Digital Design

30. Notation is Shorthand for Hardware • Consider and • Note overflow and carry registers ENG241/Digital Design

31. Logic Microoperations • OR notation a little confusing • shows two types of syntax for ORs ENG241/Digital Design

32. Shift Microoperations • Here just the basic one-bit shifts • Bit falls off the end, zero shifted in ENG241/Digital Design

33. Multiplexer-Based Transfers • There are occasions when a register receives data from two or more different sources at different times. • Recall that multiplexers are used to conditionally transfer values from the input to the output. ENG241/Digital Design

34. Multiplexer-Based Transfers • Consider • Which can also be expressed as • Block diagram? ENG241/Digital Design

35. Multiplexer Block Diagram ENG241/Digital Design

36. Detailed ENG241/Digital Design

37. Bus-Based Transfers • How about when there are lots of registers? • We can use buses and send data over common set of wires • Busses are more efficient scheme for transferring data between registers! ENG241/Digital Design

38. Bus-Based Transfers • A Bus is a shared transfer path. • It is characterized by a set of common lines usually driven by selection logic. • The control signals for the logic select a single source and one or more destinations on any clock cycle. SRC1 DEST1 DEST2 SRC2 ENG241/Digital Design

39. Simple Case: using Muxes! • Signals S1, S0 select the source • Signals L0, L1, L2 enable loading of the registers. • The single bus (on the right) can achieve more transfers than system on the left! • One mux • One output bus ENG241/Digital Design

40. Transfers • Only single source • About ½ the hardware • Select/Load Signals (table) • Limitations! ENG241/Digital Design

41. Three-State Bus • Remember three-state drivers allow having multiple outputs share wire • Note the small inverted triangle denotes the 3-state output of the register. • A bus can be constructed with the three state buffers. • Many three state buffer outputs can be connected together to form a bit line of a bus • less delay than multiplexer based systems ENG241/Digital Design

42. Same Example with 3-State • Notice that both systems in the figure have the same capability in term of transfers. • However the 3-state bus has: • Fewer wires • Easier to expand! ENG241/Digital Design

43. Memory Transfers • Usually one or more buses associated with memory • Address • Data • Note that memory can be slower, so may have to use complex timing • Address on one clock cycle • Data latched at later clock cycle ENG241/Digital Design

44. Properties of Memory • Volatile • Memory disappears if power goes out • Typical computer RAM • Static RAM (SRAM), Dynamic RAM (DRAM) • Nonvolatile • ROM • Flash memories • Magnetic memories like disk, tape ENG241/Digital Design

45. Simple View of RAM • Of some word sizen • Some capacity 2k • k bits of address line • A read line • A write line ENG241/Digital Design

46. Memory Transfer • Read: DR  M[AR] where • M denotes Memory, • DR denotes Data Register, and • AR denotes Address Register • Write: M[AR]  DR • Write: M[A1]  D2 ENG241/Digital Design

47. Memory Transfer ENG241/Digital Design

48. Data Paths --> ALU + Storage • Computer Systems often employ a number of storage elements in conjunction with a shared operation unit called an Arithmetic/Logic Unit (ALU) to form data path. • To perform a micro operation, the contents of a specified source registers are applied to the inputs of the shared ALU. • The ALU performs an operation, and the result of this operation is transferred to a destination register. ENG241/Digital Design

49. Data Paths, single clock cycle • Since the ALU is designed as a pure combinational circuit, the entire register transfer operation from the source registers, through the ALU, and into the destination register is performed in one clock cycle. ENG241/Digital Design

50. Datapath • A Simple bus-based data path: four registers, an ALU, and a shifter. • Each register is connected to two multiplexers to form ALU input buses A and B (Register File) • Another Mux is used to choose between Registers and a constant. • Functional Unit: ALU and a shifter ENG241/Digital Design