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High-Performance GPU systems and Low-cost FPGA Boards

High-Performance GPU systems and Low-cost FPGA Boards. Simon Scott UC Berkeley CASPER 2011. What happens if you place a Rhino in VEGAS?. Overview. Part 1: Architecture of VEGAS Data Acquisition System How it all Fits Together Architecture of VEGAS Data Acquisition System Testing

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High-Performance GPU systems and Low-cost FPGA Boards

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  1. High-Performance GPU systemsandLow-cost FPGA Boards Simon Scott UC Berkeley CASPER 2011

  2. What happens if you place a Rhino in VEGAS?

  3. Overview • Part 1: Architecture of VEGAS Data Acquisition System • How it all Fits Together • Architecture of VEGAS Data Acquisition System • Testing • Performance Part 2: Update on Rhino • Brief Review of Rhino Concept • Software Development • Availability • Current and Future Applications

  4. PART 1:Architecture of VEGAS HPC

  5. Acknowledgements GUPPI Developers: Paul Demorest Scott Ransom UC Berkeley Team: Hong Chen Jayanth Chennamangalam Guifre Molera Zac Rzesniowiecki Mark Wagner Dan Werthimer Large number of people at NRAO

  6. Getting Data off ROACH and onto Disk • SPEAD packets over network

  7. High Bandwidth Modes Accumulate Disk Write SamplePFBFFT X

  8. Low Bandwidth Modes Accumulate Disk Write Sample PFBFFT

  9. Inside the HPC: High BW Modes

  10. Inside the HPC: Low BW Modes

  11. Testing the Entire VEGAS Backend • High-bandwidth (non-GPU) modes: • Connect tone and noise to ADC • Check spectrum in output FITS files • Low-bandwidth (GPU-based) modes: • No ADC tests yet • FPGA transmits stored sine wave • Check spectrum in output FITS files • All looks good so far

  12. Complete Pipeline Performance

  13. Performance (2) • Whole pipeline (FPGA to disk) working at 8Gbps • 1 subband, 250MHz, 32768 pt PFB+FFT on GPU • 8 subbands, each 30MHz, 8192 pt PFB+FFT on GPU • Tricks learnt to achieve this performance: • Increase kernel UDP buffer sizes • Know your motherboard/processor architecture • Schedule threads correctly • Whole bunch of GPU memory optimizations

  14. PART 2:Update on…

  15. The Concept for Rhino • Low-cost FPGA board for radar, RA, telecomms • BORPH architecture: FPGA + processor • Xilinx Spartan-6 FPGA • Sufficient performance for most apps, but lower cost • TI ARM Cortex-A8 processor • Large support community • Open-source toolchain

  16. The Rhino Team UC Berkeley Simon Scott Centre for High-Performance Computing Alan Langman University of Cape Town Simon Winberg Brandon Hamilton Gordon Inggs Bruce Raw Saifudin Nakhwa Matthew Bridges Alastair Penny Vermeer Underground Technologies

  17. Hardware Architecture 2x 256MB DDR3 SDRAM USB, SD Card, 100Mbps Ethernet, audio and video 2x 128MB DDR2 SDRAM 256MB NAND Flash 2x FMC Connectors 2x CX4 (10Gbps ethernet)

  18. Completed Rhino Board

  19. Completed Rhino Board (2)

  20. Software Development Linux 3.1 running on ARM processor BORPH ported to Rhino Program FPGA from processor Read/write registers from processor No CASPER libraries yet for Rhino VHDL “yellow blocks” for 10 Gbps Eth, ADC interface, etc These VHDL blocks wired together in VHDL Build environment developed early 2012 ADC interface written (in VHDL) and tested: FMC150: Dual 14-bit 250MS/s ADC and DAC Interface runs at 250Mb/s per line

  21. Availability • Board tested and design stable • Rhino available from Digicom (California, USA) • Tutorials developed by UCT: • Setting-up and using Rhino • Currently used in electrical engineering courses

  22. Current Projects and Future Work • Current Rhino-related projects: • Prototyping of ground-penetrating radar using Rhino • Development of general-purpose radar DSP blocks for Rhino • Shared-memory system for networked Rhinos • 3G connectivity for Rhino for passive radar Planned Rhino projects: • Rhino Radar (L-band) • Cognitive Radar (Amit Mishra)

  23. Thank You Hardware Website www.rhinoplatform.org Git repository for Rhino software: https://github.com/brandonhamilton/rhino Rhino Tutorials https://rrsg.ee.uct.ac.za/rhinowiki

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