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A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC

A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC. Le, H.P.; Zayegh, A.; Singh, J.; Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on Volume: 2 Digital Object Identifier: 10.1109/ICECS.2003.1301824

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A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC

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  1. A 12-BIT HIGH PERFORMANCE LOW COST PIPELINE ADC Le, H.P.; Zayegh, A.; Singh, J.; Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on Volume: 2 Digital Object Identifier: 10.1109/ICECS.2003.1301824 Publication Year: 2003 , Page(s): 471 - 474 Vol.2 指導教授:易昶霈 學生:黃韋富 學號:98662001

  2. Outline • ABSTRACT • INTRODUCTION • PIPELINE ADC DESIGN • NOISE ANALYSIS OF THE PIPELINE ADC • SIMULATION RESULTS • CONCLUSION

  3. ABSTRACT • This paper presents the design and implementation of a 2.5V 12-hit high performance and low cost pipeline Analog-to-Digital converter (ADC) architecture using CMOS technology. • A modified flash ADC was employed instead of the traditional flash ADC to implement the sub-ADC in the designed pipeline ADC scheme to reduce the device complexity and attain lower system power consumption. • Such pipeline ADC is the best candidate for many applications where power and size are the major factors.

  4. INTRODUCTION • High-speed low-power Analog-to-Digital converters(ADCs) are the critical building blocks for modem communication and signal processing systems. • There has appeared a new class of ADC with an architecture known as pipeline, which offered an attractive combination of high speed, high resolution, low power dissipation and small die size.

  5. PIPELINE ADC DESIGN SHC: Sample-and-Hold Circuit

  6. NOISE ANALYSIS OF THE PIPELINE ADC

  7. SIMULATION RESULTS • DNL: differential nonlinearity. • INL: integral nonlinearity.

  8. CONCLUSION • A modified flash ADC approach has been employed to implement sub-ADCs in the designed pipeline structure to reduce the device complexity and to acquire lower device power dissipation. • It dissipates only 47.7mW of power as compared to 8O.lmW when traditional flash ADC was used, and as compared to 135 mW power consumption of the Intelligent Instrument 12-bit ADC ADS7800.

  9. Results indicate that a 40% power saving is obtained and 60% of comparators could be saved when the modified flash ADC is used instead of a full flash ADC to construct the pipeline ADC. • The developed model provides a good estimation of the noise generated by the circuit and gives an accurate prediction on the circuit noise performance.

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