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WP3 Radiation hard optical link: GBT Project

WP3 Radiation hard optical link: GBT Project. Paulo Moreira Electronics Steering Committee Meeting, White paper projects Friday 12 th March 2010 , CERN http://cern.ch/proj-gbt. Defined in the “DG White Paper” “Work Package 3-1” Objective:

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WP3 Radiation hard optical link: GBT Project

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  1. WP3Radiation hard optical link:GBT Project Paulo Moreira Electronics Steering Committee Meeting, White paper projects Friday 12th March 2010 , CERN http://cern.ch/proj-gbt

  2. Defined in the “DG White Paper” “Work Package 3-1” Objective: Development of an high speed bidirectional radiation hard optical link Deliverable: Tested and qualified radiation hard optical link Duration: 4 years (2008 – 2011) Radiation Hard Optical Link: Versatile link project: Opto-electronics Radiation hardness Functionality testing Packaging GBT project: ASIC design Verification Functionality testing Packaging On-Detector Custom Electronics & Packaging Radiation Hard Off-Detector Commercial Off-The-Shelf (COTS) Custom Protocol Radiation Hard Optical Link Architecture Paulo.Moreira@cern.ch

  3. Bandwidth: User: 3.36 Gb/s Line: 4.8 Gb/s Dedicated channels: Link control: 80 Mb/s Data/Slow control channel: 80 Mb/s DC balance: Scrambler No bandwidth penalty Forward Error Correction and Frame Synchronization Efficiency: 73% To be compared with 8B/10B: 80% no error correction capability Link is bidirectional Link is symmetrical: Down-link highly flexible: Can convey unique data to each frontend device that it is serving “Soft” architecture managed at the control room level Other schemes would require dedicated topologies that will be difficult to accommodate on a generic ASIC like the GBTX Line code and frame structure compatible with modern FPGAs GBT Link Bandwidth Paulo.Moreira@cern.ch

  4. SEU tolerant GBTX-TO-FRONTEND: E-Link Modes • GBT/Frontend interface: • Electrical links (e-link) • Serial • Bidirectional • Up to 40 links • Programmable data rate: • Independently in five groups • Independently for up/down links • 80 Mb/s, 160 Mb/s and 320 Mb/s • Lanes: • To achieve > 320 Mb/s • Two or more e-links can be grouped forming a “lane” • Slow control channel: • 80 Mb/s • E-Link: • Three pairs: DOUT/DIN/CLK • Scalable Low-Voltage Signalling (SLVS) • JEDEC standard • E-Links will be handled by E-ports: • Electrically • “Protocol” • Package (preliminary): • BGA: 361 – PINS • 16 mm x 16 mm, 0.8 mm pitch Paulo.Moreira@cern.ch

  5. Radiation tolerant chipset: GBTIA: Transimpedance optical receiver GBLD: Laser driver GBTX: Data and Timing Transceiver GBT-SCA: Slow control ASIC Supports: Bidirectional data transmission Bandwidth: Line rate: 4.8 Gb/s Effective: 3.36 Gb/s The target applications are: Data readout TTC Slow control and monitoring links. Radiation tolerance: Total dose Single Event Upsets The GBT Chipset GBTIA Data<119:0> Clock<7:0> GBTX Frontend Electronics GBLD GBT-SCA Control<N:0> Paulo.Moreira@cern.ch

  6. GBLD Main specs: • Bit rate 5 Gb/s (min) • Modulation: • current sink • Single-ended/differential • Laser modulation current: 2 to 12 mA • Laser bias: 2 to 43 mA • “Equalization” • Pre-emphasis/de-emphasis • Independently programmable for rising/falling edges • Supply voltage: 2.5 V • Die size: 2 mm × 2 mm • I2C programming interface • Packaging: • Part of the versatile link project Engineers : • Gianni Mazza – INFN, Italy • Ping Gui – SMU, USA • Angelo Rivetti – INFN, Italy • Ken Wyllie – CERN, Switzerland Status: • Chip fabricated and tested • A re-spin was necessary: • Chip submitted for fabrication: 16-Feb-2010 Paulo.Moreira@cern.ch

  7. GBLD – Test Results • GBL tests: • Chip is “functional” however the bandwidth falls short of specifications! • Fortunately the pre-emphasis circuit is working fine, allowing to partially recover the bandwidth! • The problem was identified: • Parasitic capacitance evaluation • Layout symmetry • New version: • Submitted for fabrication: 16-Feb-2010 • Pre-driver load resistance halved • Cascode transistors bulks connected to a reference voltage • Metal stack : LM → DM • Single layer aluminum inductors (higher series resistance but lower parasitic capacitance) • Voltage regulator: • Single supply voltage • PW modulation circuit removed • Pre-emphasis added on both outputs • Full symmetry • I2C controller: • ARM std cells → IBM std cells • Package: QFN 24-pin 4 mm x 4 mm • Design database : CDB → OA 2.5 Gb/s 5 Gb/s Paulo.Moreira@cern.ch

  8. GBTIA Main specs: • Bit rate 5 Gb/s (min) • Sensitivity: 20 μA P-P (10-12 BER) • Total jitter: < 40 ps P-P • Input overload: 1.6 mA (max) • Dark current: 0 to 1 mA • Supply voltage: 2.5 V • Power consumption: 250 mW • Die size: 0.75 mm × 1.25 mm Packaging: • Part of the versatile link project Engineers : • Ping Gui – SMU, USA • Mohsine Menouni – CPPM, France Status: • Chip fabricated and tested • Chip fully meets specifications! • Radiation tolerance proven! • Work has started to encapsulate the GBTIA + PIN-diode in a TO Package • (Versatile link project) Paulo.Moreira@cern.ch

  9. GBTIA – Test Results -6 dBm -18 dBm (specs: -17 dBm) Paulo.Moreira@cern.ch

  10. GBT-SERDES Engineers: Ozgur Cobanoglu - CERN, Switzerland Federico Faccio - CERN, Switzerland Rui Francisco – CERN, Switzerland Ping Gui – SMU, USA Alessandro Marchioro - CERN, Switzerland Paulo Moreira - CERN, Switzerland Christian Paillard - CERN, Switzerland Ken Wyllie - CERN, Switzerland Submitted for fabrication: 26-Nov-2009 Currently being packaged. Paulo.Moreira@cern.ch

  11. GBT-SERDES

  12. E-Links: e-port No protocol added on data stream No overhead No frame/word alignment Fixed latency Two protocols are available as possible additional MAC wrappers: 7B/8B Balanced, fixed latency, suitable for trigger commands links RTL code under development High-Level Data Link Control (HDLC) Packet oriented data, high bandwidth efficiency (~96%) Non-fixed latency, suitable for slow control and data links RTL code ready To be specified Lanes support The FE interfaces with the GBTX through ane-port The e-port handles: • The physical interface; • The multiple data rates; • The lanes (for bandwidth > 320 Mb/s) • Line coding: • Clock recovery (if required) • AC coupling (if required) The user application does not have to care about the frame formats in full detail: • It s done through a well defined interface! An E-Link Port Adaptor (EPA) “macro” will be available for integration in the front-end ASICs Engineers: • Sandro Bonacini – CERN, Switzerland • Kostas Kloukinas – CERN, Switzerland http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 12

  13. E-Link Low Power Transceiver Tests on SLVS-RT chip 1 driver 1 receiver Various types of transmission media tested: Kapton PCB Ethernet cable Test equipment Bidirectional link FPGAs perform pseudo-random data generation and checking • Receiver • Power Supply: 1.2V to 1.5V • Power Dissipation: • 150uW @ 320Mbs, 1.2V supply • <1uW @ power down • Transmitter • Power Supply: 1.2V to 1.5 V • Power Dissipation: • 3.1mW @ 320Mbs, 1.2 V supply • <10uW @ power down • Engineer • Sandro Bonacini – CERN, Switzerland (*) PRELIMINARY http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 13

  14. GBT on FPGAs GBT-SERDES successfully implemented in FPGAs: Scrambler/ Descrambler + Encoder/ Decoder + Serializer/CDR FPGA Tested: XILINX Virtex-4FX ALTERA StratixII GX Ongoing work: Optimization of use of resources Detailed implementation is device dependent Fixed and “deterministic” latency Firmware: “Starter Kit” is now available for download. Available for: StratixIIGx and Virtex5FXT Available soon for: StratixIVGx Engineers: Sophie Baron – CERN, Switzerland Jean-Pierre Cachemiche – CPPM, France Frederic Marin– CPPM, France Csaba Soos – CERN, Switzerland Xilinx - 4.8 Gb/s Altera + opto TRx - 4.8 Gb/s http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 14

  15. GBT Specifications Link specification group: • Formed in 2008 • Members: • Electronics coordinators of: • ALICE, ATLAS, CMS and LHCb • Five members of the Radiation Hard Optical Link (RHOL) project • Subsystem experts • “Mandate”: • Identify the “GBT” needs of each experiment for the SLHC upgrade • Discuss the specification documents (before they are distributed within the collaborations). • Meetings: • 1st meeting (CERN – 2008/04/17) • ALICE, ATLAS, CMS and LHCb electronics coordinators presented outlooks of their requirements for SLHC. • 2nd meeting (CERN – 2008/11/14) • GBT system proposal was presented to the electronics coordinators. • 3rd meeting (CERN – 2009/05/05) • Link specification feedback Documents: • Share point web site created (2008): • http://cern.ch/proj-gbt • Specification documents: • GBT System integration • GBTX specifications (V1.0, January 2009) • GBTIA specifications (V1.7, May 2008) • GBLD specifications (V2.0, July 2008) • GBT-SCA specifications (V1.5, June 2008) • E-Port IP 7B8B specifications (V0.1, December 2008) • E-Port IP Core specifications (V0.2, January 2009) • E-Port IP HDLC specs (V0.2, January 2009) Paulo.Moreira@cern.ch

  16. Project Schedule 2008 Design and prototyping of performance critical building blocks: GBTIA, GBLD, Serializer, De-Serializer, Phase Shifter First tests of optoelectronics components SEU tests on PIN receivers Proceed with the link specification meetings General link specification 2009 Design/prototype/test of basic serializer/de-serializer (GBT-SERDES) chip GBT-SERDES (“Tape-out” 9th of November) Design/prototype/test of optoelectronics packaging GBTIA + PIN on TO CAN 2010 GBLD re-spin GBT-SERDES testing Detailed link specification document Full prototype of optoelectronics packaging Prototype of “complete” GBTX chip 2011 Extensive test and qualification of full link prototypes System demonstrator (s) with use of full link Schedule of the final production version is strongly dependent on the evolution of the LHC upgrade schedule ! ? Paulo.Moreira@cern.ch

  17. GBT – People & Institutes LuizAmaral – CERN, Switzerland Sophie Baron – CERN, Switzerland Sandro Bonacini – CERN, Switzerland Jean-Pierre Cachemiche – CPPM, France Bruno Checcucci – INFN, Italy Jorgen Christiansen – CERN, Switzerland Ozgur Cobanoglu – CERN, Switzerland Federico Faccio – CERN, Switzerland Philippe Farthouat – CERN, Switzerland Tim Fedorov – SMU, USA Rui Francisco – CERN, Switzerland Alessandro Gabrielli – INFN, Italy TullioGrassi – University of Maryland Ping Gui – SMU, USA Paul Hartin – SMU, USA Kostas Kloukinas – CERN, Switzerland Gianni Mazza – INFN, Italy MohsineMenouni – CPPM, France Alessandro Marchioro – CERN, Switzerland Frederic Marin – CPPM, France Stefano Meroli – INFN, Italy Paulo Moreira – CERN, Switzerland Christian Paillard – CERN, Switzerland Nataly Pico – SMU, USA Antonio Ranieri – INFN, Italy Giuseppe De Robertis – INFN, Italy Angelo Rivetti – INFN, Italy Sergio Silva – CERN, Switzerland CsabaSoos – CERN, Switzerland Filipe Sousa – CERN, Switzerland Jan Troska – CERN, Switzerland Francois Vasey – CERN, Switzerland Ken Wyllie – CERN, Switzerland Bryan Yu – SMU, USA Paulo.Moreira@cern.ch

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