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Various LLRF projects FNPL Fermilab/DESY

Various LLRF projects FNPL Fermilab/DESY

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Various LLRF projects FNPL Fermilab/DESY

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  1. Various LLRF projectsFNPL Fermilab/DESY May 4th, 2005

  2. We are here LLRF Goals: I. DESY Remote control of SimCon 2.1 Cavity Simulator @ FNAL II. Again install SimCon 2.1 at A0 for local control of 9-cell Cap-Cav 1. • DESY Remote Control of 9-cell @ A0 • Build up SimCon#.# Inventory and expertise at FNAL by for Oct. CC2 test V. October SMTF test of CC2 VI. Provide several SimCon3.1 systems for 3.9 GHz stuff as well as uniform evolution

  3. I. DESY Remotely control of SimCon 2.1 Cavity Simulator @ FNAL Time Frame: currently ongoing Personnel: WK, RC, AB, TK, Status: Alexander Please put something here about Tuesdays remote work, etc

  4. II. Again install SimCon 2.1 at A0 for local control of 9-cell Cap-Cav 1. Time Frame: May 9th – 23rd Personnel: AB, TK, RC, BC, RR, (the usual suspects…) Requirements: - Brian Chase’s 2nd Vector Modulator (status ?) - SimCon2.1 and Dev5 Crate moved to back to A0 - Alexander Brandt Visits FNAL, arrives May 9th - Permanent fix for MatLab license ? We’re OK for May ONLY ! -Cave access scheduling – interlock work done, just scheduling (TK to ensure)

  5. III. DESY Remote Control of 9-cell at A0 Time Frame: May 9th – 23rd Personnel: AB, TK, BC, RC, WK…. Requirements: - Brian Chase’s 2nd Vector Modulator - SimCon2.1 and Dev5 Crate moved to back to A0 - Alexander Brandt Visits FNAL, arrives May 9th - Permanent fix for MatLab license ? We’re OK for May ONLY ! -Cave access scheduling – interlock work done, just scheduling (TK to ensure) - Alexander, Tim, present at A0 while Waldemar et. Al work at DESY. Start 3:00 AM (4:00 AM?) FNAL time

  6. III. DESY Remote Control of 9-cell at A0 After remote control is established: • 1st Need Calibrations (help from persons at FNAL, TK AB etc) • Offset compensation of vector modulator • Loop Gain, Loop Phase • Initial calibration of ADC channels of down converted signal • Port our DOOCS readout of the gradient directly to Solaris? • We need two values from DOOCS per pulse: • Maximum power from klystron • Maximum gradient during pulse. • TEST # 1: feed forward driving at different gradient • TEST # 2: feed back & feed forward • Other tests before May 23rd ?

  7. III. May 9th – 23rd SimCon2.1 A0 testSetup 1.30025GHz (square-like) VM VM VM 1.3GHz SPARC SV Timing ADCs (Control) DSP C-40 DAC ADCs (Monitoring) Function Generator SPARC LPT2VME SimCon 2.1 1.30025GHz 1.3 10MHz Wooster Crate Window+Matlab Linux

  8. IV. “Tools & System Development” Time Frame: Summer ‘05 Goals - Develop FNAL DOOCS expertise: Ron R. - Install on a development system - Upgrade A0 Day-to-Day operations (wait for Kay Rhelich’s visit) - Develop EPICS expertise at FNAL in parallel - Chris Neu - Immediately obtain another SimCon2.1 System - 2nd development crate, VME carrier board, etc - New Sparc to run DOOCS - New FNAL timing card (9/10MHz ?) - Construction of a New Master Oscillator (BC) - need Simrock to solidify frequencies (will get to later in talk) - we’ve decided to use a synthesizer as ref source (for now) - ORDER PARTS SOON !

  9. IV. “Tools & System Development” Some SimCon Definitions: SimCon2.1: Status: currently in use at IB1, to be moved to A0 Equipment: 2 ADCs 2DACs, Vertex II 3000 FPGA 3MG SimCon < 3.1 will be used with ACC1 test Status: will be used in May 23rd ACC1 test at DESY Equipment: 8 ADCs ? DACs, How does this impact us? SimCon 3.1 Status: Should be ready by August ? Equipment: 10 ADCs 4 DACs, ? FPGA

  10. IV. “Tools & system Development” FNAL’s Needed SimCon Inventory

  11. IV. “Tools & system Development” Shopping List 6 Dawn VME crates: Helen looking up previous FNAL Dawn purchase #? Timing Modules: To be specified by Mike Kucera 6 Sparcs – one for each crate: following DESY’s suggestion, Ron & Dennis 4 Motorola 5500’s (unless we determine EPICS will run on SPARCS): RR to ask Margaret 4 “client” workstations 10 MHz ADC cards for non-FPGA based monitoring - Kay Rhelich order extra10 for FNAL. URGENT to obtain a second SimCon2.1, carrier board, and FPGA development board DESY to supply: SimCon 2.1 VME Carrier Board (2 or more as to prepare for SimCon3.1) Part # for suggested FPGA development board FNAL to purchase DESY’s suggested FPGA board

  12. Distribution of Crates Crate #1: TD – DOOCS development & EPICS development populated with: SPARC, Motorola 5500, SimCon2.1 (later3.1), more to be specified Crate #2: SMTF: DOOCS for LLRF control of CC2 populated with: SPARC, Motorola 5500, SimCon2.1, more to be specified Crate #3: SMTF: Timing crate for CC2 populated with: SPARC, Motorola 5500, Timing equipment to be specified Crate #4: A0: LLRF R&D efforts populated with: SPARC, SimCon2.1 (later3.1) Crate #5: A0: Timing Crate upgrade or just 2nd? populated with: SPARC, more to be specified Crate #6: Development crate populated with: SPARC, Motorola 5500, SimCon2.1 (later3.1), more to be specified

  13. IV “Tools & system Development” New Master Oscillator Scheme (Minimum # of ports) 3900MHz (Fundamental Ref) x2 2600MHz (opt. Fundamental Ref) x2 134875MHz(LO) x5 3.9GHz Ref. 1300.250MHz (LO) x5? 1300.000MHz (Gun, CC1&2,3.9) x5 81MHz (DAC clock, LASER ?) x6 65MHz (IF or ADC Clock ?) x5? 52MHz (ADC clock ? 4/5) x5 48.75MHz (IF or ADC clock ? 4/3) x5 10MHz (timing old) x? 9MHz (timing new) x5 1MHz (DAC clock) x5 250kHz (DAC clock) x5 • Have a high frequency, low noise reference at 3.9GHz (or 2.6GHz) • Derive other frequencies using low noise dividers

  14. IV. “Tools & System Development” Understanding under-sampling Q I Q I • • • • • • 0nS 3.85nS 7.69nS 11.54nS 15.38nS 19.23nS - Q -I • 65MHz sine wave • Typically for a 65 MHz sine wave, you’d want to sample every ¼ cycle (a rate of 260MHz) and would get record I, Q, -I, -Q,I… If you undersampled at a rate of 4/5 65MHz (52MHz, T=19.23), you would get still record in the seemingly natural order: I,Q,-I,-Q,I…

  15. IV. “Tools & System Development” Understanding under-sampling Q I Q I • • • • • 0nS 5.13nS 10.26nS 15.38nS 20.51nS 25.77nS • - Q 48.75 MHz sine wave -I • • Similarly for a 48.5 MHz sine wave, you’d want to sample every ¼ cycle (a rate of 260MHz) and would get record I, Q, -I, -Q,I… If you under-sampled at a rate of 4/3 48.75 MHz (65MHz, T=15.38nS), you would record I&Q in the the order: +I,-Q,-I,+Q,I does not seem natural. Q: Which down converted frequency and ADC clock rate do we want to use ? IF at 65 MHz sampled 52MHz (4/5 natural regime) or A carrier 48.75 MHz sampled at 65MHz (4/3 regime) ? (white board showed 4/3)

  16. V. October Test of CC2 It seems prudent to develop the LLRF system for the CC2 based on SimCon2.1 (an established working board) and DOOCS as the control software. We will have the capacity to test the EPICS progress of that time. We should be able to test SimCon3.1 as well. - Plenty of crate space - New Master Oscillator - I am sure there are more features

  17. BLOCK DIAGRAM FOR MESON TEST 1.30025GHz 1.3GHz VM MO 1.30025GHz (square-like) 250 kHz 9 or 10 MHz VM ? Timing crate ADCs (Control) NEW SPARC MOTOROLA 5500 SimCon 2.1 NEW ADC (moni) Extra Module 1 Function Generator NEW SPARC MOTOROLA 5500 DSP C-40 SimCon2.1 ? Linux Linux

  18. BLOCK DIAGRAM FOR MESON TEST 1.30025GHz 1.300GHz VM MO 1.34875GHz ? 250 kHz 9 or 10 MHz 65MHz 48.75MHz Timing crate ADCs (Control) NEW SPARC MOTOROLA 5500 SimCon 3.1 NEW ADC (moni) Extra Module 1 Function Generator NEW SPARC MOTOROLA 5500 DSP C-40 ? SimCon3.1 Linux Linux