By Steve D. Wong (166/198A) Ervin Rosario-Figueroa (166/198A) Lana Dam Ivan Pierre-Louis Cuong Nguyen Spring 2003 Digital Signal Processor (DSP) San Jose State University Department of Electrical Engineering
Outline • Introduction • Specification • Project Purpose
Introduction • Design of a 4-Bit Digital Signal Processor (DSP) using CMOS Logic. • DSP is composed of a Multiplier, D Flip Flop and a Subtractor. • Up/Down Counter will be used as a test vector for the system.
Specifications • Functional Specification 4-Bit Multiplier 4-Bit Full Subtractor D Flip Flop 4-Bit Up/Down Counter • Technical Specifications Design Wn & Wp = 3 mm Power <= 0.25Watt Clock Frequency << 200 MHz VDD = 5 Volts
Schematic (4-Bit Multiplier) Schematic Layout