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Advancements in System-in-Package Testing: Strategies and Challenges

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This article discusses the complexities of System-in-Package (SiP) testing, focusing on previous work in identifying problems and solutions surrounding SiP structures. It emphasizes the need for effective test interfaces and architectures, challenges in chip-to-chip interconnections, and the importance of the IEEE P1500 standard in achieving efficient testing. Additionally, it covers future directions for improving the P1500 standard in SiP, aiming for enhanced performance and traceability within package designs. The article serves as a comprehensive overview for professionals in semiconductor testing.

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Advancements in System-in-Package Testing: Strategies and Challenges

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Presentation Transcript

  1. SiP Testing Speaker ：Meng-Syue Jhan Advisor : Chun-Yao Wang 2007/04/10

  2. Outline • Previous Work • Conclusion • Future Work

  3. Previous Work • System-in-Package Testing : Problems and Solutions • Author : Davide Appello • May-June 2006 IEEE

  4. What’s the SiP • The system-in-package(SiP) consists of multiple chips stacked and connected whthin a package • Digital computation units, memory, analog unit, power chip, and RF chip

  5. What’s the SiP (cont’d) • The main challenge to further SoC advances is the silicon technology • The components can be manufactured separately, in different technologies, and then assembled

  6. SiP test paradigm • SiP testing usually employs the known-good-die(KGD) prerequisite • The interchip connection tests and sensible-to-packaging parameter verification also needed

  7. Test structure insertion • Core test layer • DFT and test pattern • System test layer • Because SiPs have a multichip architecture, the related to the system test layer fall into several categories • Subsystem test requirements • Stacked-system test requirements • Test application

  8. Test structure insertion (cont’d) • Each manufactured chip could be itself a SoC, therefore each chip needs efficient, suitably connected interfaces and properly defined test scheduling • Chip test can exploit the overall organization and chip synergies • It’s important to consider chip-to-chip interconnect test issue

  9. Test structure insertion (cont’d) • In the test application layer, we translate the test strategy developed for the system into an ATE-readable format • Level-1 for each single chip • Level-2 for chip-to-chip interconnections and complete SiP behavior

  10. IEEE P1500 SECT • The IEEE P1500 standard for Embedded Core Test is currently one of the most cost-effective solutions for SoC testing • This standard defines • The test interface structure (wrapper) • The Core Test Language (CTL)

  11. Test access structure • Our test access solution for SiPs takes a hierarchical IEEE P1500 approach • Easy and fast to test interoperability at the core and subsystem layers • Effective support for chip-to-chip interconnection test in the same package • Definition of a standard approach for generating the chip-level and SiP-level test program

  12. SiP test strategy • Chip-to-chip interconnection test • Checks the intrasystem connectivity among the KGDs • Post-packaging test • Identifiers problems introduced by the packaging process

  13. SiP test strategy (cont’d) • Overall SiP test • Integrates the test flow with a complete functional SiP test

  14. SiP failure analysis • We should perform probing on the failed part prior to disassembly • The critical element concerns traceability

  15. Conclusion • Introducing test interfaces and architectures adds silicon area and can involve timing-performance penalties • The problem stems from dependencies between separate IP chips

  16. Future Work • How to improve P1500 on SiP

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