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SIP Testing

SIP Testing. Speaker : Meng-Syue Jhan Advisor : Chun-Yao Wang 2007/05/15. Outline. Introduction Methodology Issues Conclusion Future Work. What’s SIP. The system-in-package(SiP) consists of multiple chips stacked and connected whthin a package

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SIP Testing

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  1. SIP Testing Speaker : Meng-Syue Jhan Advisor : Chun-Yao Wang 2007/05/15

  2. Outline • Introduction • Methodology • Issues • Conclusion • Future Work

  3. What’s SIP • The system-in-package(SiP) consists of multiple chips stacked and connected whthin a package • Digital computation units, memory, analog unit, power chip, and RF chip • The components can be manufactured separately, in different technologies, and then assembled

  4. Advantage & Disadvantage • Advantage • Easy to design • Dies can be manufactured separately • Batter performance、smaller dimensions and lower power etc • Disadvantage • Testing problems • Testing knowledge transfer • Known good die(KGD)

  5. Methodology • Design for test (DFT) • Involves test points that provide additional contacts on the exterior of package • Available space to route those additional test points • Additional routing or test points would impact performance or yield of the SIP

  6. Methodology (cont’d) • Built-in self test (BIST) • Involves embedding test circuitry in the chip at the design phase • Because of cost, not every die suppiler has BIST in their design • It’s well-suited for some logic and memory applications, but with radio frequency device, difficulties arise

  7. Methodology (cont’d) • Package on package (PoP) • One way to address the limitations of KGDs • We can encapsulate some dies into the package • It’s easier to handle than bare dies • But packaged dies have bigger size • Allows high-yielding devices to be assembled together in one package, and lower-yielding devices to be assembled in a sparate package

  8. Methodology (cont’d) • The IEEE P1500 • standard for Embedded Core Test is currently one of the most cost-effective solutions for SoC testing • This standard defines • The test interface structure (wrapper) • The Core Test Language (CTL)

  9. Our idea • We could use P1500 and PoP technology on SIP testing

  10. Issue • Interconnections testing • Because the defects usually occur on interconnection • How to test interconnections • Testing economic • Cost-effective • 0/1 Knaspack problem

  11. How to test interconnection • Assume these dies have P1500’s architecture Bare die Bare die TAM

  12. Problem of interconnection testing • Consider this situation ？ ？ TAM

  13. 0/1 knaspack problem • Given the set S = {1…n}, where item i has size Si and value Vi • Find the subset of S which maximizes the value of S

  14. An example • Assume total capacity is 50 10 20 30 30 30 $60 20 $100 20 $120 10 10 $160 $180 $220

  15. Conclusion • We can learn the algorithm of 0/1 knaspack problem to solve cost-effective problem • Trade-off between die size and die yield

  16. Future work • Solve the interconnection testing problem • Read SIP testing papers

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