ECE 3110: Introduction to Digital Systems

1. ECE 3110: Introduction to Digital Systems Multiple-outputs minimization Timing Hazards

2. Previous… • PoS minimization • Don’t care values

3. Multiple-Output Minimization • Most digital applications require multiple outputs derived from the same input variables. • Example: 3 inputs and 2 outputs • Each output function could be minimized using K-map and realized independently. • The output functions could share one or more product terms (prime implicant) which reduces the total number of gates. X F1 Y Logic Circuit F2 Z

4. Example • F1= XZ+YZ’ F2=XY’+YZ’ • To find the common terms multiply the two functions (F1.F2) • The common terms are : YZ’, XY’Z XY X XY X 00 01 11 10 Z 00 01 11 10 Z 0 2 6 4 0 2 6 4 0 0 0 1 1 0 0 1 1 1 1 3 7 5 1 3 7 5 1 1 Z Z 0 0 1 1 0 0 0 1 Y Y XY X Z 00 01 11 10 0 2 6 4 0 0 1 1 0 1 3 7 5 1 Z 0 0 0 1 Y

5. Example - Logic Diagram • Independent realization Minimal realization F1= XZ+YZ’ F2= XY’+YZ’ F1 F1 X Y X F2 Z Y F2 Z

6. Real-World Logic Design More than 6 inputs -- can’t use Karnaugh maps Design correctness more important than gate minimization Use “higher-level language” to specify logic operations Use programs to manipulate logic expressions and minimize logic. PALASM, ABEL, CUPL -- developed for PLDs VHDL, Verilog -- developed for ASICs

7. Timing Hazards • The Truth Table determines the Steady State behavior of a Combinational Logic Circuit • Transient behavior: - Output could produce glitches (a short pulse) when input variables change.- Glitches occur when the paths between inputs and output have different delays.- Timing Hazards refer to the possibility of having glitches during input transitions. • Hazards :- Definitions.- Finding hazards. - Eliminating hazards.

8. Definitions • Static Hazards:* Static-1 Hazard : Two input combinations that : - differ in only one variable . - both produce logic 1 . - possibly produce Logic 0 glitch during input variable transition * Static-0 Hazard : Two input combinations that - differ in only one variable - Both produce logic 0 - Possibly produce Logic 1 glitch during input variable transition • Dynamic hazards: - The output could change more than once during input transitions- Caused by multiple paths with different delays from input to the output 1 0 1 0

9. X Y Z Z’ YZ XZ’ F glitch T Example • F= YZ+XZ’ • Delay in each gate is T . • Input changes from XYZ=111 to 110 Y F Z X

10. Finding Timing hazards using K-map • Two-level AND-OR Circuits : • Static 0 hazards do not exist in the sum-of products (AND-OR) implementation. • Static 1 hazards are possible • The K-map of the function F in the previous example :- Cell 6 ( 110 ) and cell 7 ( 111 ) are covered in two product terms XY X Faster 00 01 11 10 Z Y 1 1 0 0 2 6 4 F Z 1 0 0 0 0 1 1 0 1 1 0 1 1 3 7 5 1 X 1 Z 0 1 1 0 Static 1 hazard Y

11. Timing hazards in OR-AND circuits • Static 1 hazards do not exist in the Product-of sums (Two-level OR-AND) implementation. • Static 0 hazards are possible • The minimal product of F = ( X+Z)(Y+Z’)- Cell 0 ( 000 ) and cell 1 ( 001 ) are covered in two sum terms- Static 0 hazard occurs when inputs switched between 000 to 001 Faster XY X 00 01 11 10 X 0 0 1 Z F Z 0 1 0 2 6 4 0 0 0 1 1 1 0 0 1 0 Z Y 0 1 3 7 5 1 0 1 1 0 Static 0 hazard Y

12. Eliminating Timing Hazards • AND-OR Circuit- Add a prime implicant that combines the two inputs that cause static 1 hazard.---->consensus- Cells 6 & 7 are combined : XY • The hazard-free circuit is : XY X 00 01 11 10 Z Y 1 1 0 0 2 6 4 0 0 1 1 1 F Z 1 0 1 1 3 7 5 1 Z 0 1 1 1 X 1 0 1 1 Y

13. Eliminating Timing Hazards • OR-AND Circuit- Add a prime implicant that combines the two inputs that cause static 0 hazard.---->consensus- Cells 0 & 1 are combined : X+Y • The hazard-free circuit is : XY X 00 01 11 10 Z 0 2 6 4 X 0 0 1 0 0 0 1 1 F Z 0 1 0 Z 1 0 1 3 7 5 1 0 1 1 0 Y 0 0 Y

14. Summary • A properly designed two-level SOP (AND-OR) circuit has no static-0 hazards. It may have static-1 hazards. • A properly designed two-level POS (OR-AND) circuit has no static-1 hazards. It may have static-0 hazards. • Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit. It may occur in multilevel circuits. • A brute-force method of obtaining a hazard-free realization is to use the complete sum or complete product. • Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits.