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Advanced ASIC Development at UCSB HEP Group: SPDT Transmission Gate Progress Report

This report outlines the progress made on SPDT Transmission Gate development by the UCSB HEP Group. It covers the creation of 12x6.75um cells with various color codes for different components, highlighting the Analog Transmission Gate. The report includes details on PIXEL usage, area allocation, and future plans for expanding the cell library with NMOS, PMOS transistors, NAND Gate, NOR Gate, and D.Flip.Flop designs.

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Advanced ASIC Development at UCSB HEP Group: SPDT Transmission Gate Progress Report

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  1. 5x5 Pixel Array Status4 February 2004 Sam Burke Sean Stromberg UCSB HEP Group

  2. ASIC Progress • SPDT Analog Transmission Gate Created

  3. SPDT Transmission Gate

  4. SPDT Transmission Gate • 12x6.75um cell • Blue: Metal1 • Red: Poly1 • Green: Active • Pink: P+ • Yellow: N Well • Lt Green:Active • Blk squares: Contact • Wht #1: Via1 • Gray: Metal2 • Note: N+ not drawn?

  5. SPDT Trans Gate Net List

  6. Transmission Gate • Transient Response • Tlh=59ps • Thl=154ps

  7. PIXEL Usage • 250 um Pixel Size • Area=250^2=62500 um^2 • 18 bit Counter 18*498=8964 um^2 (14%) • Analog Circuits 10,000 um^2 est (16%) • Misc. Glue Logic (7%) • 10 Inverters 10*54= 540 um^2 • 8 DFFR 8*498= 3984 um^2 • Unused Area 62500-23488=39012 um^2 (62%)

  8. PIXEL Area Usage

  9. Future Plans • Continue creating new Cell Library • NMOS & PMOS Transistors • Inverter1 (done) • Transmission Gate (done) • NAND Gate • NOR Gate • D Flip Flop • D Flip Flop with Clear

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