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Challenges in Hybrid DSP/FPGA Implementations of Optimal Beamforming Bogdan Vacaliuc, Sundance DSP, Inc.

Challenges in Hybrid DSP/FPGA Implementations of Optimal Beamforming Bogdan Vacaliuc, Sundance DSP, Inc. Overview. Company Highlights and Background BF1 System Requirements Top Level Design Partitioning Case Studies Current Status Future Expansion Options. Sundance.

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Challenges in Hybrid DSP/FPGA Implementations of Optimal Beamforming Bogdan Vacaliuc, Sundance DSP, Inc.

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  1. Challenges in Hybrid DSP/FPGA Implementations of Optimal Beamforming Bogdan Vacaliuc, Sundance DSP, Inc.

  2. Overview • Company Highlights and Background • BF1 System Requirements • Top Level Design • Partitioning • Case Studies • Current Status • Future Expansion Options

  3. Sundance • Established 1989, Privately held Company; Assets in excess of $2M • Sundance Design, Manufacturing, Test in England and USA; Sales Offices around the World • Sundance is ISO9100-2000 compliant company and has been since 1998.

  4. World Leading Users • Michigan Tech University • SPAWAR Systems Center - Charleston • Lockheed Martin • Cymer • NASA • Raytheon • TRW • General Dynamics • Philips Medical • Motorola • L3-Communication • Lucent Technologies • MIT • Rolls Royce • ...

  5. Module Carriers PCI cPCI VME PMC Modules A/D,D/A,I/O DSP,FPGA IMAGING,MEMORY Systems • Data Acquisition • Medical • Industrial Control • & Monitoring Concept of Modular Design

  6. Processing modules SMT398 SMT318-SX55 SMT361Q SMT374-300 • Dual Xilinx XC4VSX55-12 • 1024 XtremeDSP • 1.6GB/s inter-FPGA I/O • 2.5GB/s I/O bandwidth • Xilinx Virtex II XC2V8000-4 • 4MB ZBT SRAM • 2MB QDR SRAM • 1.6GB/s I/O bandwidth • Dual 300 MHz TI C6713 • Xilinx Virtex II XC2V2000-4 • 256MB SDRAM • 920MB/s I/O bandwidth • Quad TI C6416 • Xilinx Virtex II XC2V2000-4 • 4MB internal memory • 920MB/s I/O bandwidth

  7. cPCI SMT300Q PCI SMT310Q Platforms Embedded SMT180 VME SMT328

  8. Company Highlights and Background • BF1 System Requirements • Top Level Design • Partitioning • Case Studies • Current Status • Future Expansion Options

  9. BF1 System Requirements • Digital System for processing 8 element ULA or UCA (receiver only) • Target Signal: Family Radio Service (FRS) • 462.5625MHz to 467.7125MHz • 25KHz channel separation • Intermediate Frequency • 21.4MHz Center • 22.5MHz Bandwidth • Able to separate “talkers” on the same frequency • USB 2.0 Interface to HOST

  10. BF1 System Requirements (cont.) • Flexibility in implementing different beamforming algorithms • Flexibility in implementing different channel (de)modulation algorithms • Multi-Channel operation required • The more channels, the better

  11. Company Highlights and Background • BF1 System Requirements • Top Level Design • Partitioning • Case Studies • Current Status • Future Expansion Options

  12. Tuner ADC Top Level Design Channelizer • A tuner for each antenna • An ADC for each tuner • One channelizer • A beamformer/demodulator for each channel Beamformer Demodulator Output to Host

  13. ADC Selection • Fs > 75MHz • Fs > 2*(IFcenter+(IFspan/2)+Guard) • Ideal Fs is 102.4MHz • Fs = Fc*M M= # FFT points • Fc = 25KHz • M is > 3000 for Fs > 75MHz • Pick 4096 point FFT, Fs = 102.4MHz • Maximize #ADC per module • Maximize ADC resolution • Pick SMT364 • Quad 105MSPS ADC • 14-bit resolution

  14. CLOCK Selection • Need to synchronize 8 ADCs (or more) • On board clock is not synchronized between all ADCs • Each pair of ADCs are clocked together • SMT364 requires two external clocks per module • For beamforming it is essential to have high stability clock sources that do not drift over time • MOST IMPORTANT component

  15. CLOCK Selection (cont.) • Evaluate oscillator performance by considering phase noise tables • Estimate RMS jitter and compute absolute maximum SNR • Make sure maximum SNR >> ADC specification [1] Computed from the on-line calculator at: http://www.raltron.com/cust/tools/osc.asp [2] SNR = 20log10(1/(2*PI*Fsignal*Tjitter)) as described in: http://www.analog.com/en/content/0,2886,760%255F788%255F91502,00.html

  16. External Clock (build option) 4-way Power Splitter < 3° phase variance SMT399-F102.4 Module Amplifier with phase adjustment MMBX or SMA (build option) • Fixed Frequency Clock Source • Frequency Stability: 50ppb • Aging: 300ppb/year • Option for external clock input On-board linear regulator and power filter MMCX (build option) Flexible power input (TIM or EXT) Fine Frequency adj. for calibration

  17. System Level – Analog Connections

  18. ADC Correction and Normalization • Parameters (offset, gain, delay) • Offset • For BF1 System each ADC is channelized independently, so offset not a problem • For systems that interleave ADC to increase the effective sampling rate it is critical • Gain • Can be adjusted by ADC parameter • Can be adjusted numerically • Numerical adjustment is easier • Delay • ADCs can start at slightly different clock edges (even with a trigger pulse distribution)

  19. Design Level – ADC block detail FC201 for ADC channel correction FC202 for quadrature conversion • Common handling (in FPGA firmware) of all channels • Prepares data stream for channelization

  20. Company Highlights and Background • BF1 System Requirements • Top Level Design • Channelization • Case Studies • Current Status • Future Expansion Options

  21. Channelization • Polyphase Filter • Each channel represents a frequency band • M is chosen with respect to Fs (102.4MHz) and channel spacing (25KHz) • In the BF1 System • Fs is 102.4MHz • M is 4096 • Provides 4096 channels @25KSPS

  22. Channel Partitioning and Distribution • Bandwidth problem • 8 * 4 * 102.4MHz is 3.2GB/sec • No module has that amount of I/O capacity • Separate channels based on region of interest. • Beamforming is done on each channel separately • Combine output from all ADCs • On different FPGAs in our system

  23. Channel Partitioning (cont.) • Use an FC108 block for each ADC input • FC108-D is a double-data rate version of FC108 • Fits onto XC4VSX55 • 220MHz with -12 part • FC203A exchanges high/low channels and ADC streams • FC203B formats the selected channels into a multiplexed “frequency domain highway”

  24. FDMA Highway • Enables distribution of multiple channels from all ADCs to other modules • 40us frame time represents the channel spacing (25KHz) • (FC202 decimated Fs by 2 with no loss of spectral information)

  25. Putting it all together…

  26. Software and Firmware Development -Simulink/Matlab -C Reference Models Modeling -PARS -System Generator -Diamond + CCS + ISE Code & Build -Debugger,Simulator -Data I/O, Scripting -Hardware In The Loop Debug -Real Time Analysis -Profiling (CCS) -Timing (GPIO) Analyze & Tune

  27. Develop System Model Tasks & Channels

  28. Generate System Firmware Map onto hardware

  29. MATHWORKSTM SimulinkTM PARS System Generator Code Composer StudioTM Traditional VHDL Development Tools Software Level 2 Level 1 Sundance Target Hardware SMT319 with Xilinx Virtex II XC2V2000-4

  30. Photo of Initial Prototype System

  31. ? Roadmap • System-System Interconnects • Expand on number of ADC channels • Enable additional antennas • PARS Enhancements • Use HDL Coder to enable Simulink->FPGA • Increasingly automatic code generation • Sundance will lead in modular, deployable signal processing

  32. Thank You

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