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Timer/Counter

Timer/Counter. Pulse Width Modulation modes. There are two PWM modes of Timer/Counter 0. PWM mode is determined by bits WGM00:WGM01 1:1 – Fast PWM mode Timer/Counter counts from 0x00 to 0xFF After reaching 0xFF, rolls over to 0x00 and starts over 1:0 – Phase Correct PWM mode

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Timer/Counter

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  1. Timer/Counter Pulse Width Modulation modes CS-280 Dr. Mark L. Hornick

  2. There are two PWM modes of Timer/Counter 0 PWM mode is determined by bits WGM00:WGM01 • 1:1 – Fast PWM mode • Timer/Counter counts from 0x00 to 0xFF • After reaching 0xFF, rolls over to 0x00 and starts over • 1:0 – Phase Correct PWM mode • Timer/Counter counts from 0x00 to 0xFF to 0x00 • After reaching 0xFF, decrements back down to 0x00 and starts over CS-280 Dr. Mark L. Hornick

  3. In both PWM modes, the T/C counts all the way to MAX Counter value MAX= 0xFF OCR0 BOTTOM = 0x00 Fast PWM Mode ticks Counter value MAX= 0xFF OCR0 BOTTOM = 0x00 PWM Phase Correct Mode ticks CS-280 Dr. Mark L. Hornick

  4. Output Comparator behavior in PWM Modes Output Comparator can drive the voltage on OC0 (PB3) high or low • PB3 must be setup for output When in PWM modes, bits COM01:COM00 affect the operation as follows: • 0 0: OC0 disconnected • 0 1: Reserved • 1 0: Clear OC0 on compare match • 1 1: Set OC0 on compare match CS-280 Dr. Mark L. Hornick

  5. Signals on OC0 in Fast PWM mode Counter value MAX= 0xFF OCR0 BOTTOM = 0x00 Fast PWM Mode ticks COM01:COM00 = 1:1 Set OC0 on compare match COM01:COM00 = 1:0 Clear OC0 on compare match ticks Signal on OC0 CS-280 Dr. Mark L. Hornick

  6. Fast PWM Interrupts • OCF0 flag in TIFR is set when TCNT0=OCR0. When OCIE0 is enabled: • Compare Match interrupt is generated (ISR jump vector at 0x14) • OCF0 is automatically reset when ISR is executed • TOV0 is set when TCNT0 overflows from 0xFF to 0. When TOIE0 is enabled: • Overflow interrupt is generated (ISR jump vector at 0x16) • TOV0 is automatically reset when ISR is executed CS-280 Dr. Mark L. Hornick

  7. The duration of pulse width can be modulated by varying the value of OCR0 CS-280 Dr. Mark L. Hornick

  8. Behavior of OC0 in PWM Phase Correct mode Counter value MAX= 0xFF OCR0 BOTTOM = 0x00 PWM Phase Correct Mode ticks COM01:COM00 = 1:1 Set OC0 on compare match COM01:COM00 = 1:0 Clear OC0 on compare match ticks Signal on OC0 CS-280 Dr. Mark L. Hornick

  9. Phase-correct Interrupts • OCF0 flag in TIFR is set when TCNT0=OCR0. When OCIE0 is enabled: • Compare Match interrupt is generated (ISR jump vector at 0x14) • OCF0 is automatically reset when ISR is executed • TOV0 is set when TCNT0 decrements back to 0. When TOIE0 is enabled: • Overflow interrupt is generated (ISR jump vector at 0x16) • TOV0 is automatically reset when ISR is executed CS-280 Dr. Mark L. Hornick

  10. Pulse width modulation in Phase-correct operation CS-280 Dr. Mark L. Hornick

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