Csci 136 Computer Architecture II – A Pipelined Datapath

1. Csci 136 Computer Architecture II– A Pipelined Datapath Xiuzhen Cheng cheng@gwu.edu

2. Announcement • Homework assignment #9, Due time –Before class, April 05. • Readings: Sections 6.1 – 6.3 • Problems: 6.1-6.4, 6.13-6.14 • Project #3 is due on April 10, 2005

3. Topics • Two pipelined datapath representations • Single cycle • Multiple cycle • Five functional units for pipelined datapath • Each can be used only within a single pipeline stage. Why? • Comparison of single cycle datapath, multi cycle datapath and pipelined datapath • From one to another • Sharing of functional unit • Number of clock cycles • Clock cycle time • Temporary registers – pass information • Complexity of control design ( hazards… )

4. Graphically Representing Pipelines multiple-clock-cycle pipeline datagrams • Can help with answering questions like: • how many cycles does it take to execute this code? • what is the ALU doing during cycle 4? • use this representation to help understand datapaths

5. Pipelined Datapath

6. Single Cycle Datapath

7. Multi Cycle Datapath

8. Single-Cycle Pipeline Datagram • What do we need to add to split the datapath into stages?

9. Pipelined Datapath • how many bits stored in each pipeline register? 64 128 64 97

10. Observations • 5-stage pipeline • IF, ID, EX, MEM, WB • Left-to-right flow of instructions • Instructions and data move generally from left to right • Two exceptions: WB stage and the selection of PC • May lead to data hazards and control hazards • Why there is no pipeline register at the end of the WB stage? • Last stage must update either register file, or memory, or PC

11. 1st lw Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Pipelining the Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 • The five independent functional units in the pipeline datapath are: • Instruction Memory for the Ifetch stage • Register File’s Read ports (busA and busB) for the Reg/Decstage • ALU for the Exec stage • Data Memory for the Mem stage • Register File’s Write port (bus W) for the Wr stage Clock 2nd lw 3rd lw

12. Ifetch Reg/Dec Exec Wr The Four Stages of R-type Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: • ALU operates on the two register operands • Wr: Write the ALU output back to the register file R-type

13. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Pipelining the R-type and Load Instruction • We have pipeline conflict or structural hazard: • Two instructions try to write to the register file at the same time! • Only one write port Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock Oops! We have a problem! R-type R-type Load R-type R-type

14. 1 2 3 4 5 Load Ifetch Reg/Dec Exec Mem Wr 1 2 3 4 R-type Ifetch Reg/Dec Exec Wr Important Observation • Each functional unit can only be used once per instruction • Each functional unit must be used at the same stage for all instructions: • Load uses Register File’s Write Port during its 5th stage • R-type uses Register File’s Write Port during its 4th stage • 2 ways to solve this pipeline hazard

15. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Solution 1: Insert “Bubble” into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 • Insert a “bubble” into the pipeline to prevent 2 writes at the same cycle • The control logic can be complex • Lose instruction fetch and issue opportunity • No instruction is started in Cycle 6! Clock Load R-type Pipeline R-type R-type Bubble

16. Ifetch Reg/Dec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Solution 2: Delay R-type’s Write by One Cycle • Delay R-type’s register write by one cycle: • Now R-type instructions also use Reg File’s write port at Stage 5 • Mem stage is a NOOPstage: nothing is being done 4 1 2 3 5 Exec Mem R-type Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type R-type

17. Ifetch Reg/Dec Exec Mem The Four Stages of Store Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: Calculate the memory address • Mem: Write the data into the Data Memory Store Wr

18. Ifetch Reg/Dec Exec The Three Stages of Beq Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: • Registers Fetch and Instruction Decode • Exec: • compares the two register operand, • select correct branch target address • latch into PC Mem Beq Wr

19. Pipelined Execution of Load Instruction

20. Pipelined Execution of Load Instruction

21. Pipelined Execution of Load Instruction

22. Pipelined Execution of Load Instruction

23. Pipelined Execution of Load Instruction

24. Pipelined Execution of Store Instruction

25. Pipelined Execution of Store Instruction

26. Observations from Load and Store • Pass information needed from an earlier stage to a latter stage • Each logical component of the datapath – such as IM, Reg read ports, ALU, DM, Reg write port – can be used only within a single pipeline stage. Otherwise, we would have structural hazard • A bug in the pipelined datapath for load. Can you tell?

27. Modified Datapath – For Basic R-Type, LW/SW, and BEQ

28. Pipelined Execution for Multiple Instructions

29. Pipelined Execution for Multiple Instructions

30. Pipelined Execution for Multiple Instructions

31. Pipelined Execution for Multiple Instructions

32. Pipelined Execution for Multiple Instructions

33. Pipelined Execution for Multiple Instructions

34. Pipelined Datapath Control

35. op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<N:0> “R-type” Or Add Add xx Subtract Overview on Datapath Control • For the subset of instructions under consideration, N=1. • ALUOp = 00 for Add, 01 for Sub, and 10 for R-type

36. Observations • No write control for all pipeline registers and PC since they are updated at every clock cycle. • To specify the control for the pipeline, set the control values during each pipeline stage. • Control lines can be divided into 5 groups: • IF – NONE • ID – NONE • ALU – RegDst, ALUOp, ALUSrc • MEM – Branch, MemRead, MemWrite • WB – MemtoReg, RegWrite • Group these nine control lines into 3 subsets: • ALUControl, MEMControl, WBControl • Control signals are generated at ID stage, how to pass them to other stages?

37. Pass Control Signals • Extend the pipeline registers to include control information

38. The Complete Pipelined Datapath

39. Example Pipeline Execution • Show the five instructions going through the pipeline: lw $10, 20($1) sub $11, $2, $3 and $12, $4, $5 or $13, $6, $7 add $14, $8, $9 Note that these instructions are independent with each other!

40. Clock1

41. Clock2

42. Clock3

43. Clock4

44. Clock5

45. Clock6

46. Clock7

47. Clock8

48. Clock9

49. Questions?