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This paper discusses the Multiplexed Redundant Execution (MRE) technique as a solution for efficient fault tolerance in chip multiprocessors (CMPs). CMPs face challenges like soft errors and wear-out-related permanent faults as they become prevalent for performance growth. MRE involves a leading core pool for applications requiring fault tolerance, a trailing core pool for similar applications, and a non-redundant core pool. Experimental results show that MRE achieves better average performance degradation (2%) compared to traditional fault tolerance methods (<18%).
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Paper Report Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors PramodSubramanyan, Virendra Singh Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India Kewal K. Saluja Electrical and Computer Engg. Dept., University of Wisconsin-Madison, Madison, WI Erik Larsson Dept. of Computer and Info. Science, Linkoping University, Linkoping, Sweden Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 Cite count: 16 Presenter: Jyun-Yan Li
What’s the problem • Chip multiprocessors (CMPs) become the major for performance growth • Susceptible to soft errors, wear-out related permanent fault … • 2 cores or thread contexts execute single program in the CMP • Throughput loss • The throughput of the CMP decreases to half • System cost • Cooling, energy and maintenance cost
Proposal method • Multiplexed Redundant Execution (MRE) • Leading core pool • Executing applications that require fault tolerance • Trailing core pool • Executing applications that require fault tolerance • 3th pool • Non-redundant applications
Experimental result • Workload: 9 applications form the SPEC2000 • Reducing input set by the MinneSPEC • Average Performance • MRE degrades 2% • CRT degrades 18%