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EECS 150 - Components and Design Techniques for Digital Systems Lec 25 – Division & ECC

EECS 150 - Components and Design Techniques for Digital Systems Lec 25 – Division & ECC. David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150. Division.

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EECS 150 - Components and Design Techniques for Digital Systems Lec 25 – Division & ECC

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  1. EECS 150 - Components and Design Techniques for Digital Systems Lec 25 – Division & ECC David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150

  2. Division 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result) • At each step, determine one bit of the quotient • If current “remainder” larger than division, subtract and set Q bit to 1 • Otherwise, bring down a bit of the dividend and set Q bit to 0 • Dividend = Quotient x Divisor + Remainder sizeof(dividend) = sizeof(quotient) + sizeof(divisor) • 3 versions of divide, successive refinement EECS 150, Fa04, Lec 25-div & errors

  3. 32-bit DIVIDE HARDWARE Version 1 • 64-bit Divisor register, 64-bit adder/subtractor, 64-bit Remainder register, 32-bit Quotient register Shift Right Divisor 64 bits Shift Left Quotient add/sub 32 bits Write Remainder Control 64 bits EECS 150, Fa04, Lec 25-div & errors

  4. 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right 1 bit. Done Start: Place Dividend in Remainder Divide Alg. Version 1 n+1 steps for n-bit Quotient & Rem. Remainder Quotient Divisor000001110000 00100000 710 210 Remainder < 0 Remainder 0 Test Remainder No: < n+1 repetitions n+1 repetition? Yes: n+1 repetitions (n = 4 here) EECS 150, Fa04, Lec 25-div & errors

  5. Example: initial condition Shift Right 0010 0000 Divisor Shift Left 0000 add/sub Quotient Write 0000 0111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  6. Example: iter 1, step 1 • 1: rem <= rem – div; [7 – 32 --> -25] • Check rem <0? Shift Right 0010 0000 Divisor Shift Left 0000 add/sub Quotient Write 11100111 0000 0111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  7. Example: iter 1, step 2b • rem <= rem + div; • Shift Q left, bringing in 0 Shift Right 0010 0000 Divisor Shift Left 0000 add/sub Quotient Write 00000111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  8. Example: iter 1, step 3 • Shift div right Shift Right 00010000 Divisor Shift Left 0000 add/sub Quotient Write 00000111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  9. Example: Iter 2, Steps 1,2b,3 • 1: rem <= rem – div; [7 – 16 --> -9] • 2. check rem <0? rem <= rem + div; sll Q, Q0=0 • 3. srl div Shift Right 00010000 00001000 Divisor Shift Left 0000 0000 add/sub Quotient Write 00000111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  10. Example: Iter 3, Steps 1,2b,3 • 1: rem <= rem – div; [7 – 8 --> -1] • 2. check rem <0? rem <= rem + div; sll Q, Q0=0 • 3. srl div Shift Right 00000100 Divisor Shift Left 0000 add/sub Quotient Write 00000111 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  11. Example: Iter 4, Steps 1,2a,3 • 1: rem <= rem – div; [7 – 4 --> 3] • 2. check rem <0? sll Q, Q0=1 • 3. shr div Shift Right 00000100 00000010 Divisor Shift Left 0001 0000 add/sub Quotient Write 00000111 00000011 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  12. Example: Iter 5, Steps 1,2a,3 • 1: rem <= rem – div; [3 – 2 --> 1] • 2. check rem <0? sll Q, Q0=1 • 3. shr div Shift Right 00000010 00000001 Divisor Shift Left 0011 0001 add/sub Quotient Write 0000 0011 00000001 Control Remainder/Dividend EECS 150, Fa04, Lec 25-div & errors

  13. Version 1: Division 7/2 Iteration step quotient divisor remainder 0 Initial values 0000 0010 0000 0000 0111 1 1: rem=rem-div 0000 0010 0000 1110 0111 2b: rem<0  +div, sll Q, Q0=0 0000 0010 0000 0000 0111 3: shift div right 0000 0001 0000 0000 0111 2 1: rem=rem-div 0000 0001 0000 1111 0111 2b: rem<0  +div, sll Q, Q0=0 0000 0001 0000 0000 0111 3: shift div right 0000 0000 1000 0000 0111 3 1: rem=rem-div 0000 0000 1000 1111 1111 2b: rem<0  +div, sll Q, Q0=0 0000 0000 1000 0000 0111 3: shift div right 0000 0000 0100 0000 0111 4 1: rem=rem-div 0000 0000 0100 0000 0011 2a: rem0  sll Q, Q0=1 0001 0000 0100 0000 0011 3: shift div right 0001 0000 0010 0000 0011 5 1: rem=rem-div 0001 0000 0010 0000 0001 2a: rem0  sll Q, Q0=1 0011 0000 0010 0000 0001 3: shift div right 0011 0000 0001 0000 0001 EECS 150, Fa04, Lec 25-div & errors

  14. Observations on Divide Version 1 • 1/2 bits in divisor always 0 1/2 of 2n-bit adder is wasted 1/2 of 2n-bit divisor is wasted • Instead of shifting divisor to right, shift remainder to left? • 1st step cannot produce a 1 in quotient bit (otherwise quotient  2n) switch order to shift first and then subtract, can save 1 iteration EECS 150, Fa04, Lec 25-div & errors

  15. DIVIDE HARDWARE Version 2 • 32-bit Divisor register, 32-bit ALU, 64-bit Remainder register, 32-bit Quotient register Divisor 32 bits Shift Left Quotient 32 bits add/sub Shift Left Remainder Control Write 64 bits EECS 150, Fa04, Lec 25-div & errors

  16. 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. 3a. Shift the Quotient register to the left setting the new rightmost bit to 1. Done Start: Place Dividend in Remainder Divide Alg. Version 2 Remainder Quotient Divisor 000001110000 0010 710 210 Remainder  0 Remainder < 0 Test Remainder nth repetition? No: < n repetitions Yes: n repetitions (n = 4 here) EECS 150, Fa04, Lec 25-div & errors

  17. Example V2: 7/2 initial conditions Divisor 0010 Shift Left 0000 Quotient add/sub Shift Left 00000111 Control Write Remainder EECS 150, Fa04, Lec 25-div & errors

  18. Example V2: 7/2 iter 1 • 1. Shift left rem • 2. sub: remLH <- remLH – div [0 – 2] • Test remLH < 0 • 3b restore remLH <- remLH + div • Shift 0 into Q Divisor 0010 Shift Left 0000 0000 Quotient add/sub Shift Left 00001110 11101110 00001110 00000111 Control Write Remainder EECS 150, Fa04, Lec 25-div & errors

  19. Announcements • Dec 9, last day of class will do HKN survey • Final mid term: Dec 15 12:30 – 3:30 in 1 LECONTE • EECS in the news • Recovery Oriented Computing • Joint with Stanford! • Availability = MTBF / (MTBF + Time to Repair) • Historically focus on increasing MTBF • ROC focuses on reducing Time to Restart: • Isolation and Redundancy • System-wide support for Undo • Integrated Diagnostic Support. • Online Verification of Recovery Mechanisms. • Design for high modularity, measurability, and restartability.  • Dependability/Availability Benchmarking. Dave Patterson EECS 150, Fa04, Lec 25-div & errors

  20. Observations on Divide Version 2 • Eliminate Quotient register by combining with Remainder as shifted left. • Start by shifting the Remainder left as before. • Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half • The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many. • Thus the final correction step must shift back only the remainder in the left half of the register EECS 150, Fa04, Lec 25-div & errors

  21. DIVIDE HARDWARE Version 3 • 32-bit Divisor register, 32-bit adder/subtractor, 64-bit Remainder register, (0-bit Quotient reg) Divisor 32 bits 32-bit ALU “HI” “LO” Shift Left (Quotient) Remainder Control Write 64 bits EECS 150, Fa04, Lec 25-div & errors

  22. Start: Place Dividend in Remainder 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. Done. Shift left half of Remainder right 1 bit. Divide Algorithm Version 3 Remainder Divisor0000 0111 0010 710 210 Remainder < 0 Remainder  0 Test Remainder *upper-half No: < n repetitions nth repetition? Yes: n repetitions (n = 4 here) EECS 150, Fa04, Lec 25-div & errors

  23. Observations on Divide Version 3 • Same Hardware as shift and add multiplier: just 63-bit register to shift left or shift right • Signed divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary • Note: Dividend and Remainder must have same sign • Note: Quotient negated if Divisor sign & Dividend sign disagreee.g., –7 ÷ 2 = –3, remainder = –1 EECS 150, Fa04, Lec 25-div & errors

  24. Error Correction Codes (ECC) • Memory systems generate errors (accidentally flipped-bits) • DRAMs store very little charge per bit • “Soft” errors occur occasionally when cells are struck by alpha particles or other environmental upsets. • Less frequently, “hard” errors can occur when chips permanently fail. • Problem gets worse as memories get denser and larger • Where is “perfect” memory required? • servers, spacecraft/military computers, ebay, … • Memories are protected against failures with ECCs • Extra bits are added to each data-word • used to detect and/or correct faults in the memory system • in general, each possible data word value is mapped to a unique “code word”. A fault changes a valid code word to an invalid one - which can be detected. EECS 150, Fa04, Lec 25-div & errors

  25. Error changes bit pattern to non-code Sparse population of code words (2M << 2N) - with identifiable signature Correcting Code Concept • Detection: bit pattern fails codeword check • Correction: map to nearest valid code word Space of possible bit patterns (2N) EECS 150, Fa04, Lec 25-div & errors

  26. Each data value, before it is written to memory is “tagged” with an extra bit to force the stored word to have even parity: Each word, as it is read from memory is “checked” by finding its parity (including the parity bit). b7b6b5b4b3b2b1b0p b7b6b5b4b3b2b1b0p + + c Simple Error Detection Coding Parity Bit • A non-zero parity indicates an error occurred: • two errors (on different bits) is not detected (nor any even number of errors) • odd numbers of errors are detected. • What is the probability of multiple simultaneous errors? EECS 150, Fa04, Lec 25-div & errors

  27. Use more parity bits to pinpoint bit(s) in error, so they can be corrected. Example: Single error correction (SEC) on 4-bit data use 3 parity bits, with 4-data bits results in 7-bit code word 3 parity bits sufficient to identify any one of 7 code word bits overlap the assignment of parity bits so that a single error in the 7-bit work can be corrected Procedure: group parity bits so they correspond to subsets of the 7 bits: p1 protects bits 1,3,5,7 p2 protects bits 2,3,6,7 p3 protects bits 4,5,6,7 1 2 3 4 5 6 7 p1 p2 d1 p3 d2 d3 d4 Bit position number 001 = 110 011 = 310 101 = 510 111 = 710 010 = 210 011 = 310 110 = 610 111 = 710 100 = 410 101 = 510 110 = 610 111 = 710 p1 p2 p3 Hamming Error Correcting Code Note: number bits from left to right. EECS 150, Fa04, Lec 25-div & errors

  28. Example: c = c3c2c1= 101 error in 4,5,6, or 7 (by c3=1) error in 1,3,5, or 7 (by c1=1) no error in 2, 3, 6, or 7 (by c2=0) Therefore error must be in bit 5. Note the check bits point to 5 By our clever positioning and assignment of parity bits, the check bits always address the position of the error! c=000 indicates no error eight possibilities 1 2 3 4 5 6 7 p1 p2 d1 p3 d2 d3 d4 Note: parity bits occupy power-of-two bit positions in code-word. On writing to memory: parity bits are assigned to force even parity over their respective groups. On reading from memory: check bits (c3,c2,c1) are generated by finding the parity of the group and its parity bit. If an error occurred in a group, the corresponding check bit will be 1, if no error the check bit will be 0. check bits (c3,c2,c1) form the position of the bit in error. Hamming Code Example EECS 150, Fa04, Lec 25-div & errors

  29. Interactive Quiz 1 2 3 4 5 6 7 positions 001 010 011 100 101 110 111 P1 P2 d1 P3 d2 d3 d4 role • You receive: • 1111110 • 0000010 • 1010010 • What is the correct value? Position of error = C3C2C1 Where Ci is parity of groupi EECS 150, Fa04, Lec 25-div & errors

  30. Overhead involved in single error correction code: let p be the total number of parity bits and d the number of data bits in a p + d bit word. If p error correction bits are to point to the error bit (p + d cases) plus indicate that no error exists (1 case), we need: 2p >= p + d + 1, thus p >= log(p + d + 1) for large d, p approaches log(d) 8 data => 4 parity 16 data => 5 parity 32 data => 6 parity 64 data => 7 parity Adding on extra parity bit covering the entire word can provide double error detection 1 2 3 4 5 6 7 8 p1 p2 d1 p3 d2 d3 d4 p4 On reading the C bits are computed (as usual) plus the parity over the entire word, P: C=0 P=0, no error C!=0 P=1, correctable single error C!=0 P=0, a double error occurred C=0 P=1, an error occurred in p4 bit Hamming Error Correcting Code Typical modern codes in DRAM memory systems: 64-bit data blocks (8 bytes) with 72-bit code words (9 bytes). EECS 150, Fa04, Lec 25-div & errors

  31. Summary • Arithmetic • Addition, subtraction, multiplication, & division follow the rules you learned as a child, but in base 2 • Iterative Multiplication and Division are essentially same circuit • Clever book keeping so n-bit add/sub using n-bit register and 2n-bit shift register • tricks to avoid sub/check/add restore??? • See “Booth’s Alg” tricks below for multiply (if time) • Error coding • Map data word into larger code word • Hamming distance is number of bit flips between symbols • Parity detects errors of hamming distance 1 • Overlapping parity detects 2 and corrects 1 (SECDED) EECS 150, Fa04, Lec 25-div & errors

  32. Motivation for Booth’s Algorithm • Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 • If ALU can subtract as well as add, get same result as follows: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 • For example 0010 x 0110 0000 shift (0 in multiplier)– 0010 sub(first 1 in multiplier)0000 shift (mid string of 1s) + 0010 add (prior step had last 1) 00001100 EECS 150, Fa04, Lec 25-div & errors

  33. Booth Multiplier: an Introduction • Recode each 1 in multiplier as “+2-1” • Converts sequences of 1 to 10…0(-1) • Might reduce the number of 1’s 0 0 1 1 11 1 1 0 0 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 0 1 0 0 0 0 0 -1 0 0 EECS 150, Fa04, Lec 25-div & errors

  34. Recoding (Encoding) Example • If you use the last row in multiplication, you should get exactly the same result as using the first row (after all, they represent the same number!) 0 1 1 0 111 0 0 0 1 0 (+1 -1) (+1 -1) (+1 -1) (+1 -1)(+1 -1) (+1 -1) +1 0 -1 +1 0 0 -1 0 0 +1 -1 0 EECS 150, Fa04, Lec 25-div & errors

  35. Sign extension Booth Multiplication Example 0 0 1 1 0 6x 0 1 1 1 0 14 +1 0 0 -1 0 0 0 0 0 0 1 1 0 1 0 (-6) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 84 1 1 1 EECS 150, Fa04, Lec 25-div & errors

  36. Booth’s Alg: Implementation Approach end of run beginning of run Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift is faster than add, it is advantageous to replace adds and subs with shifts) Basic idea: replace a string of 1s in multiplier with an initial subtract for rightmost 1 in a run of 1’s, then later add back a 1 for the bit to the left of the last 1 in the run middle of run 0 1 1 1 1 0 –1 + 10000 01111 EECS 150, Fa04, Lec 25-div & errors

  37. Booth’s Example (2 x 7) Operation Multiplicand Product next? 0. initial value 0010 0000 01110 10 -> sub 1a. P = P - m 1110 + 1110 1110 01110 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done EECS 150, Fa04, Lec 25-div & errors

  38. Booth’s Example (2 x -3) Operation Multiplicand Product next? 0. initial value 0010 0000 11010 10 -> sub 1a. P = P - m 1110 +1110 1110 11010shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 111 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done EECS 150, Fa04, Lec 25-div & errors

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