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The BaBar Silicon Vertex Tracker

The BaBar Silicon Vertex Tracker. Owen Long University of California, Santa Barbara for the BaBar Collaboration. PEP-II and the BaBar Experiment. Physics Objective: CP violation in B meson decays. Overdetermine the parameters of the CKM quark mixing matrix. Experimental Approach:

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The BaBar Silicon Vertex Tracker

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  1. The BaBar Silicon Vertex Tracker Owen Long University of California, Santa Barbara for the BaBar Collaboration Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  2. PEP-II and the BaBar Experiment • Physics Objective: • CP violation in B meson decays. • Overdetermine the parameters of the CKM quark mixing matrix. • Experimental Approach: • High-luminosity e+e- collider with Upsilon(4s) center-of-mass energy. • B and anti-B mesons produced coherently. • CP asymmetries depend on Dt between B decays. • Time-integrated CP asymmetries vanish. • Measurement of B decay points is essential. • Asymmetric beam energies boost Upsilon(4s) in lab (bg=0.56). e- beam direction Dz Upsilon(4s) decay point B0 decay point B0 decay point Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  3. SVT Institutions • USA: • Lawrence Berkeley National Laboratory • Stanford University • University of California, Santa Barbara • University of California, Santa Cruz • University of California, San Diego • University of Wisconsin • Italy: • Ferrara • Milan • Pavia • Pisa • Torino • Trieste Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  4. SVT Design Requirements and Constraints • Performance Requirements • Dz resolution < 130 mm. • Single vertex resolution < 80 mm. • Stand-alone tracking for Pt < 100 MeV/c. • PEP-II Constraints • Permanent dipole (B1) magnets at +/- 20 cm from IP. • Polar angle restriction: 17.20 < Q < 1500. • Must be clam-shelled into place after installation of B1 magnets • Bunch crossing period: 4.2 ns (nearly continuous interactions). • Radiation exposure at innermost layer (nominal background level): • Average: 33 kRad/year. • In beam plane: 240 kRad/year. • SVT is designed to function in up to 10 X nominal background. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  5. The BaBar Silicon Vertex Tracker • 5 Layers of double-sided, AC-coupled Silicon. • Custom rad-hard readout IC (the AToM chip). • Low-mass design. ( Pt < 2.7 GeV/c2 for B daughters) • Stand-alone tracking for slow particles. • Inner 3 layers for angle and impact parameter measurement. • Outer 2 layers for pattern recognition and low Pt tracking. 20 cm 30 cm 40 cm Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  6. Space Frame and Support Cones Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  7. SVT Geometry LayerRadius 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm Be Beam pipe 1.0 % X0 10 cm (Arched wedge wafers not shown) Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  8. SVT Modules Z-Side High Density Interconnect (mechanical model) Flexible Upilex Fanout Micro-bonds Micro-bonds Phi-Side Carbon/Kevlar fiber Support ribs Si Wafers • Fanout Properties: • < 0.03 % X0 • 0.52 pF/cm Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  9. Ringframe Fixtures Ringframes protect Si wafers and High Density Interconnects (HDIs) during testing. • “Parking lot” on Fanout enables • wafer tests without bonding. • Bonds for strips with faults plucked • before bonding to HDI. • Fanout is cut, glued, and bonded • to HDI after wafer testing. • 1/2 modules are tested again • before module assembly. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  10. SVT High Density Interconnect Flexible Tail (testing version) • Functions: • Mounting and cooling • for readout ICs. • Mechanical mounting point • for module. Berg Connector Mounting Buttons • Features: • AlN substrate. • Double sided. • Thermistor for temp. monitor. • 3 different models. AToM Chips Upilex Fanout Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  11. Silicon Wafers • Features: • Manufactured at Micron. • 300 mm thick. • 6 different wafer designs. • n- bulk, 4-8 kW cm. • AC coupling to strip implants. • Polysilicon Bias resistors on wafer, 5 MW. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  12. Silicon Wafers Edge guard ring P-stop n+ Implant 55 mm Polysilicon bias resistor p+ Implant Bias ring Al 50 mm Polysilicon bias resistor Edge guard ring p+ strip side n+ strip side Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  13. Measured Wafer Characteristics • Strip Properties • n-siden-side n-side p-side • Strip Pitch: 50 mm55 mm 105 mm 50 mm • Inter-strip C: 1.1 pF/cm 1.0 pF/cm 1.0 pF/cm 1.1 pF/cm • AC decoupling C: 20 pF/cm 22 pF/cm 34 pF/cm 43 pF/cm • Implant-to-back C: 0.19 pF/cm 0.36 pF/cm 0.17 pF/cm • Bias R: 4 to 8 MW 4 to 8 MW 4 to 8 MW 4 to 8 MW • Bulk Properties • Bias current: 0.1 to 1.0 mA • Bulk current: 0.1 to 1.0 mA • Depletion voltage: 35 to 45 V Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  14. Detector-Fanout Assemblies • Status: • All wafers are glued to fanouts, bonded, and tested. • Over 0.3 million bonds. • Fault Types: • Pinhole - Break in the AC coupling capacitor, short between metal and implant. • P-stop short (DC) - Bond foot breaks through oxide layer shorting metal and p-stop. • High current (DC) - Low value for bias resistor. • Unbondable - Damaged or obstructed bond pad, rework not possible. Fault Channels Pinhole 1 - 2 % DC-fault 1 - 2 % Other 1 % Total faults: 2 - 4 % Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  15. The AToM Chip AToM = ATime Over threshold Machine 5.7 mm • Custom Si readout IC designed for BaBar by: • LBNL • INFN-Pavia • UCSC • Features: • 128 Channels per chip • Rad-Hard CMOS process (Honeywell) • Simultaneous • Acquisition • Digitization • Readout • Sparsified readout • Time Over Threshold (TOT) readout • Internal charge injection 8.3 mm Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  16. The AToM Chip Sparsification Readout Buffer Chan # CAC TOT Counter Time Stamp PRE AMP 15 MHz Shaper Comp Buffer Si Revolving Buffer 193 Bins Event Time Event Number Thresh DAC Buffer CAL DAC CINJ Serial Data Out • TOT, Tstamp, Buffering • 4 bits TOT (logarithmic) • 5 bits Hit Tstamp • (67 ns/count) • 4 buffers / channel • Amp, Shape, Discr, Calib • 5-bit CAL DAC (0.5 fC/count) • 5-bit Thr DAC (0.05 fC/count) • Shaping time 100 - 400 ns • Trigger Latency Buffer • 15 MHz Sample rate • Total storage = 12.7 us Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  17. Threshold Scan • Procedure • Fix charge injection value • Scan Threshold DAC (0-63) • 1 Threshold DAC count = 10.5 mV • 10.5 mV/count / Gain = 0.053 fC / count • Fit Hit efficiency vs Threshold to Error Function • Width = Noise • 50% point = Offset for Qinj Hits Noise Threshold Offset • Gain Measurement • 3 threshold scans at different Qinj values • Fit 50% point vs Qinj • Slope is Gain (Dthr/DQ in mV/fC) • Intercept is Threshold DAC offset Offset Counts Threshold DAC Offset Qinj Counts Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  18. TOT and Charge Scan • Scan calibration DAC (0-63) at a fixed threshold. • Range of injected charge: 0 to 30 fC (1 MIP = 3.8 fC) • Measure Time Over Threshold (TOT) response. • Hit TOT stored in 4 bits (1-15). Injected Charge (fC) Injected Charge (fC) 1 MIP 1 MIP Time Over Threshold Time Over Threshold CAL DAC CAL DAC Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  19. Measured Noise and Gain • 100 ns200 ns 400 ns • AToM-I, test board: 450 ele + 47 ele/pF 375 ele + 45 ele/pF 325 ele + 39 ele/pF • AToM-II, test board: 350 ele + 40 ele/pF 275 ele + 35 ele/pF 225 ele + 26 ele/pF • AToM-I, Layer 2 mod: • Phi-side 1350 ele 1200 ele 1050 ele • Z-side 1050 ele 850 ele 750 ele • AToM-I, Gain: 190 mV/fC 235 mV/fC 200 mV/fC • AToM-II, Gain: 300 mV/fC • Total strip capacitance ranges from 11 to 37 pF. • Threshold setting of 4 X Noise still well below 1 MIP ( about 20,000 ele ). Chip Properties Threshold offset dispersion: 14 mV or 440 ele Chip power consumption: 0.57 W/chip, 4.5 mW/chan AToM-II measurements are preliminary. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  20. AToM IC and Wafer Characteristics After Exposure to Radiation • AToM-I Chip • After exposure to 2.4 MRad with Co60 source • Gain dropped 0 to 20 % • Power off during exposure Power on during exposure • C=0dNoise/dCC=0dNoise/dC • Noise Increase 15 to 80 % 15 to 50 % 5 to 10 % < 5% • Only 3 chips tested. Will check this result with more tests. • Silicon Wafers • After exposure to 1 MRad of photons from a Co60 source • <17% increase in interstrip capacitance • Current density <350 nA/cm2, mostly generation at Si - insulator surface Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  21. Production and Construction • Silicon Wafers: • All wafers in hand. • Wafers glued to fanouts, bonded, and tested. • Front-End Electronics: • High Density Interconnect (HDI) substrate production nearly complete. • 2 lots of AToM-I in hand. AToM-II testing underway. • Several HDIs loaded, tested, and bonded to detectors. • Mechanical: • Support cones, space frame, and mounting rings complete. • Ready to begin module assembly. • Back-End Electronics: • Production complete. Loading and testing. • Estimated date of completion: Early March 1999. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  22. PEP-II at SLAC • The PEPII Collider at SLAC • Luminosity: 3 x 1033 to 1034 cm-2 s-1 • 30 to 100 million Upsilon(4s) per year. • Beams collided head-on (no crossing angle). • Bunch crossing period: 4.2 ns • Interactions effectively continuous. • Permanent dipole magnets required • close to interaction point. Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  23. SVT Mechanical Features Brass cooling rings Carbon fiber Space Frame 22 cm B1 dipole permanent magnet (inside support cone) B1 dipole permanent magnet (inside support cone) Carbon fiber support cones 109 cm Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  24. SVT Mechanical Features Silicon wafers Carbon & Kevlar fiber support ribs Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  25. SVT Modules Number of Wafers Total Phi-Strip Length Backward Forward Layer Z-Strip Length 5b 8 26.5 cm 26.5 cm 4.1 to 5.1 cm 5a 8 26.5 cm 25.1 cm 4.2 to 5.1 cm 4b 7 22.4 cm 19.9 cm 4.2 to 5.1 cm 4a 7 22.4 cm 18.5 cm 4.2 to 5.1 cm 3 6 12.8 cm 12.8 cm 7.0 cm 2 4 8.8 cm 8.8 cm 4.8 cm 1 4 8.2 cm 8.2 cm 4.0 cm Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  26. Silicon Wafers P-Stops • Features: • Manufactured at Micron. • 300 mm thick. • 6 different wafer designs. • n- bulk, 4-8 kW cm. • AC coupling to strip implants. • Polysilicon Bias resistors • on wafer, 5 MW. n- Bulk n+ Implant Readout Pitch Aluminum Strip Pitch Silicon dioxide n- Bulk p+ Implant Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  27. Wafer Specifications Used in Layers 1,2, and 3 Used in Layers 4 and 5 Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  28. Phi Side Readout Pitch, 1-3 • Phi side is 30 - 100 % half bonded • due to E x B effect. • 100 to 110 mm readout pitch • where charge is spread over • more strips. • 50 to 55 mm readout pitch • where charge is focused on • fewer strips. 50 mm Pitch 100 mm Pitch • Compromise between • Hit efficiency • Signal to noise ratio • and • Hit resolution • 2-Track resolution Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  29. SVT Data Transmission • HDI: High Density Interconnect. Mounting fixture • and cooling for readout ICs. • Kapton Tail: Flexible multi-layer circuit. Power, • clock, commands, and data. • Matching Card: Connects dissimilar cables. • Impedance matching. • HDI Link: Reference signals to HDI digital common. • DAQ Link: Multiplex control, demultiplex data. • Electrical -- optical conversion. Power Supplies Back Cables MUX Power Front Cables HDI Link Matching Card Si Wafers HDI Kapton Tail DAQ Link Fiber Optic to DAQ Owen Long, UCSB VERTEX ‘98 Santorini, Greece

  30. Calibration • Internal charge injection used for • Measuring Gain, Noise, and Threshold Offsets • Identifying shorts and bad channels • Examining Time Over Threshold (TOT) response • Testing digital functionality • Charge injection circuit • 5-bit DAC (0-63) • 1 DAC count = 0.48 fC • Range 0 - 30 fC (1 MIP = 4 fC) • Calibration methods • Threshold scan (Gain, Noise, Offsets) • Charge scan (TOT response) Owen Long, UCSB VERTEX ‘98 Santorini, Greece

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