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Infrastructure and Testing Update for T&C Boards and Calorimeter Status

The infrastructure for the T&C boards is nearly complete, with 10 T&C boards and 16 slots in L3VRCa currently operational. The T&C controller is projected to be ready in about six weeks, with 10 out of 12 quadrants instrumented. We aim to complete 250 BLS boards at a rate of 50 per week, with most of the CC debugged. Additionally, we are addressing ECS trigger issues in CCSW and testing ongoing. Fine adjustments to the calorimeter are expected soon, incorporating new FPGA code for enhanced performance metrics.

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Infrastructure and Testing Update for T&C Boards and Calorimeter Status

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  1. Status Almost all infrastructure in place 10 T&C boards, 16 slots in L3VRCa. T&C controller still ~6 weeks 10/12 quadrants instrumented. 250 BLS boards to go, 50/week CC mostly debugged (1% level), working on ECS Trigger summers/drivers in CCSW 64 BLS cards (towers) = 2/3 quadrant Should get ½-full CC next week? Testing (10-20 hr)+ stuffing (50 hr) Ordering parts (resistors) for EC’s Run Plan Time relative to TFW using pulser and trigger pickoffs to get the same bunch #. Don’t need beam. We cog with TFW to correct place for master clock Compare L1 trigger energy and precision readout (gains are off a bit as Run 1 hardware at first) Fine adjustments need new FPGA code to triple sample (~ 2 weeks) Calorimeter Status and PlansMar-Apr 2001

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