1 / 12

Digital Hadron Calorimeter Status

Digital Hadron Calorimeter Status. Jos é Repond Argonne National Laboratory. CALICE Technical Board Meeting DESY February 25 – 26, 2005. Virtually all R&D on chambers completed. Active Detectors: RPCs. Pick-up pads. Graphite. Signal. HV. Gas. Resistive plates.

tara
Télécharger la présentation

Digital Hadron Calorimeter Status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digital Hadron Calorimeter Status José Repond Argonne National Laboratory CALICE Technical Board Meeting DESY February 25 – 26, 2005

  2. Virtually all R&D on chambers completed Active Detectors: RPCs

  3. Pick-up pads Graphite Signal HV Gas Resistive plates Default RPC chamber designs

  4. Active Detectors: GEMs R&D on GEMs not as advanced as for RPCs

  5. Electronic Readout System for Prototype Section 400,000 readout channels Conceptual design of system I Front-end ASIC II Data concentrator III VME data collection IV Trigger and timing system

  6. Front-end ASIC… 64 inputs with choice of input gains RPCs (streamer and avalanche), GEMs… Triggerless or triggered operation 100 ns clock cycle Output: hit pattern and time stamp ASIC performance specified in 41 page document Design almost complete (FNAL) Submission in March

  7. Front-end boards… Design challenge Data concentrators… 8 layer boards Each housing 24 ASICs Overall thickness < 3 mm Contains both analog and digital signals Readout 12 ASICs Located on sides of section Essentially FPGAs

  8. Data collector… Initiated design effort Pursuing two possibilities a) PCI links with switch b) VME-based system

  9. List of subtasks

  10. Cost estimate (M&S only)… $500,000 + 50% contingency $375,000 + 50% contingency

  11. Recent Proposals to Funding Agencies…

  12. Time scales Tune Hadron Simulation

More Related