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Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective. Designing Sequential Logic Circuits. Naming Conventions. In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edge-triggered elements flip-flops

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective Designing SequentialLogic Circuits

  2. Naming Conventions • In our text: • a latch is level sensitive • a register is edge-triggered • There are many different naming conventions • For instance, many books call edge-triggered elements flip-flops • This leads to confusion however

  3. Latch versus Register • Latch stores data when clock is low • Register stores data when clock rises D Q D Q Clk Clk Clk Clk D D Q Q

  4. Latch-Based Design • N latch is transparentwhen f = 0 • P latch is transparent when f = 1 f N P Logic Latch Latch Logic

  5. Timing Definitions CLK Register t D Q t t su hold D DATA CLK STABLE t t c q 2 Q DATA STABLE t

  6. CLK D D CLK Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state (can implement as NMOS-only) Converting into a MUX

  7. Q 0 Q 1 D 1 D 0 CLK Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK

  8. Edge-Triggered Flip-flop

  9. Static SR Flip-Flop Clock version? Writing data by pure force No clock needed (Asynchronous)

  10. Registers for Pipelining

  11. Registers for Pipelining ? Pipelined

  12. Semiconductor Memories

  13. Memory • Memory Classification • Memory Architectures • The Memory Core • Periphery

  14. Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM

  15. Memory Timing: Definitions

  16. Decoder reduces the number of select signals K = log N 2 Memory Architecture: Decoders M bits M bits S S 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A cell cell 1 words A N K 1 Decoder 2 S N 2 2 Word N 2 Word N 2 2 2 S N 1 2 Word N 1 Word N 1 2 2 K log N 5 2 Input-Output Input-Output ( M bits) ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals

  17. Array-Structured Memory Architecture

  18. Hierarchical Memory Architecture

  19. Read-Only Memory Cells (ROM) BL BL BL VDD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2

  20. MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads

  21. MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

  22. MOS NOR ROM Layout Cell (9.5l x 7l) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion

  23. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

  24. No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM MOS NAND ROM Layout Cell (8l x 7l) Programmming using the Metal-1 Layer Only Polysilicon Diffusion Metal1 on Diffusion

  25. Precharged MOS NOR ROM V f DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

  26. D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section

  27. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V 2 2 S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming

  28. FLOTOX EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim I-V characteristic FLOTOX transistor

  29. V DD EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

  30. Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide 1 1 n source n drain programming p- substrate Many other options …

  31. Cross-sections of NVM cells Flash EPROM Courtesy Intel

  32. Characteristics of State-of-the-art NVM

  33. Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

  34. Q 6-transistor CMOS SRAM Cell WL V DD M M 2 4 Q M M 6 5 M M 1 3 BL BL

  35. CMOS SRAM Analysis (Read) WL V DD M BL 4 BL Q 0 = M Q 1 = 6 M 5 V V V M DD DD DD 1 C C bit bit

  36. WL V DD M 4 M Q 0 = 6 M 5 Q 1 = M 1 V DD BL 1 BL 0 = = CMOS SRAM Analysis (Write)

  37. VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL 6T-SRAM — Layout

  38. Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2

  39. SRAM Characteristics

  40. BL 1 BL 2 WWL WWL RWL RWL M 3 V V X M X 2 DD T 1 M 2 V DD BL 1 C S V D BL 2 V V 2 DD T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V -V WWL Tn 3-Transistor DRAM Cell

  41. BL2 BL1 GND RWL M3 M2 WWL M1 3T-DRAM — Layout

  42. 1-Transistor DRAM Cell

  43. DRAM Cell Observations • 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. • DRAM memory cells are single ended in contrast to SRAM cells. • The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. • Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. • When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value thanVDD

  44. V V (1) BL V PRE D V (1) V (0) t Sense amp activated Word line activated Sense Amp Operation

  45. Metal word line SiO 2 Poly Field Oxide Diffused + + n n bit line Inversion layer Poly Polysilicon induced by Polysilicon plate plate bias gate Capacitor 1-T DRAM Cell M word 1 line Cross-section Layout

  46. Periphery • Decoders • Sense Amplifiers

  47. Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

  48. Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL 0 A A A A A A A A A A A A A A A A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 0 0 1 3 2 2 3

  49. V DD V DD V DD V DD Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 V A A A A f DD 0 0 1 1 A A A A f 0 0 1 1 2-input NAND decoder 2-input NOR decoder

  50. BL BL BL BL 0 1 2 3 S 0 A 0 S 1 S 2 A S 1 3 D 4-input pass-transistor based column decoder 2-input NOR decoder Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count

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