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Digital Integrated Circuits A Design Perspective

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malha
80 diapositives · 1.2K Views · Sep 19, 2014

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Inverter. July 30, 2002. V. DD. V. V. in. out. C. L. The CMOS Inverter: A First Glance. Q.Why was CMOS invented? A.For large signal swing at the output.

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  1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter July 30, 2002

  2. V DD V V in out C L The CMOS Inverter: A First Glance Q.Why was CMOS invented? A.For large signal swing at the output. Q.Why wasn’t it popular right after its birth? A.Process complexity, large gate size. Q.Why is it now so popular? A.Power, power, power… Now CMOS is fast, small, reliable and… the only solution for SoC, AND expected to be so for coming Xx years.

  3. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  4. Two Inverters *Same height, different width-> Share power and ground *Vertical pitch matching-> Abut cells Connect in Metal W/L ratio Multiple contact windows

  5. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp)

  6. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n V 0 V V = = in DD in (a) Low-to-high (b) High-to-low Where does load cap. come from? How is Ron determined?

  7. Static CMOS 의 특성 • Load device; active, no body effect (no bulk bias) • Same number of PFET’s as NFET’s (complementary inter-connection) • Full Vdd swing • Ratioless logic -> always provides low output impedance cf. ratioed logic -> Low out value is not loe enough, and high Zo for high output value cf. tri-state buffer -> Three output values(?)

  8. Voltage TransferCharacteristic

  9. Homework #2 (Insight into R,L,C) • For each of RC, RL, RLC (two types-bandpass and notch filter) circuit, do the following(assume reasonable values so that you observe what you(and Prof. Kyung) would want from this work (due Nov. 5); • Apply a step function and analyze (interpret) the SPICE result. • Apply a delta function and analyze (interpret) the SPICE result. • Obtain the frequency characteristics.

  10. I Dn V = V +V in DD GSp I = - I Dn Dp V = V +V out DD DSp V out I I I Dp Dn Dn V =0 V =0 in in V =1.5 V =1.5 in in V V V DSp DSp out V =-1 GSp V =-2.5 GSp V = V +V V = V +V in DD GSp out DD DSp I = - I Dn Dp PMOS Load Lines

  11. CMOS Inverter Load Characteristics

  12. CMOS Inverter VTC

  13. 1.8 This is for short-channel (velocity-saturated) device. What about the long-channel device? (prob 5.1) 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Switching Threshold as a function of Transistor Ratio, r

  14. V out V OH V M V in V OL V V IL IH Determining VIH and VIL A simplified approach

  15. Inverter Gain

  16. Gain=-1 Gain as a function of VDD Vth = 0.5 V Subthreshold operation Transistor still worksfor Vdd approaching Vth. Vdd must be at least 2 to 4 times thermal voltage. Reducing Vdd improves the gain, while the switching speed becomes low.

  17. Simulated VTC

  18. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  19. Propagation Delay

  20. CMOS Inverter Propagation DelayApproach 1

  21. CMOS Inverter Propagation DelayApproach 2

  22. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  23. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpLH tpHL

  24. Design for Performance • Keep capacitances small • Increase transistor sizes • watch out for self-loading! • Increase VDD (????)

  25. Delay as a function of VDD

  26. Device Sizing See equ (5.28) For large S, tp Approaches Intrinsic or unloaded delay, tp0. (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  27. NMOS/PMOS ratio for cascaded inverter for minimal average delay tpHL tpLH tp b = Wp/Wn Optimal beta for rising/falling Symmetry is 2.4, while it is 1.9 considering the self-loading Of PMOS(higher than 1.6 as predicted by equ. 5.26 in text).

  28. Impact of Rise Time on Delay ?

  29. Inverter Sizing

  30. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

  31. Inverter Delay • Minimum length devices, L=0.25mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpHL = (ln 2) RNCL Delay (D): tpLH = (ln 2) RPCL Load for the next stage:

  32. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1

  33. Inverter with Load CP = 2Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

  34. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

  35. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

  36. Optimal Tapering for Given N • Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • each stage has the same effective fanout (Cout/Cin) • each stage has the same delay

  37. Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay

  38. Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages:

  39. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

  40. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1

  41. Impact of Self-Loading on tp No Self-Loading, g=0 With Self-Loading g=1

  42. Normalized delay function of F

  43. Buffer Design N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 64 16 1 64 22.6 8 2.8

  44. Power Dissipation

  45. Where Does Power Go in CMOS?

  46. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

  47. Modification for Circuits with Reduced Swing

  48. Adiabatic Charging 2 2 2

  49. Adiabatic Charging

  50. Node Transition Activity and Power