Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Designing CombinationalLogic Circuits November 2002.

2. CL Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

3. CL Solution to Charge Leakage Keeper Clk Mp Mkp A Out B Clk Me Same approach as level restorer for pass-transistor logic

4. CL CA CB Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out A B=0 Clk Me

5. CL CA Charge Sharing Clk VOut A VX B=0 Clk Slide by Kia

6. CL CA Charge Sharing Clk VOut A VX B=0 Clk Slide by Kia

7. Charge Sharing V DD M Clk p Out C L M A a X C a M = B 0 b C b M Clk e

8. Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

9. CL1 CL2 Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2 =0 In A=0 B=0 Clk Me Dynamic NAND Static NAND

10. Backgate Coupling Effect Out1 Voltage Clk Out2 In Time, ns

11. CL Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out A B Clk Me

12. Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk Voltage In4 Out Clk Time, ns Clock feedthrough

13. Other Effects • Capacitive coupling • Substrate coupling • Minority charge injection • Supply noise (ground bounce)

14. Clk In VTn Out1 V Out2 Cascading Dynamic Gates V Clk Clk Mp Mp Out2 Out1 In Clk Clk Me Me t Only 0  1 transitions allowed at inputs!

15. Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me

16. Properties of Domino Logic • Only non-inverting logic can be implemented • Very high speed • static inverter can be skewed, only L-H transition • Input capacitance reduced – smaller logical effort • Better noise margin

17. Ini Ini Ini Ini PDN PDN PDN PDN Inj Inj Inj Inj Why Call it Domino? Clk Clk Like falling dominos!

18. Footer needed? Clk Clk Out2 Out1 In Clk Clk Slide by Kia (fig by Rabaey)

19. Designing with Domino Logic V V DD DD V DD Clk M Clk M p p M r Out1 Out2 In 1 PDN In PDN In 2 4 In 3 Can be eliminated! M Clk M Clk e e Inputs = 0 during precharge

20. Footless Domino The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current A solution is to delay the clock for each stage

21. Domino Layout Slide by Kia

22. np-CMOS Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

23. NORA Logic Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me to other PDN’s to other PUN’s WARNING: Very sensitive to noise!

24. Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B Clk Me Solves the problem of non-inverting logic

25. Multiple-Output Domino