CMPT 334 Computer Organization

1. CMPT 334 Computer Organization Midterm I Review

2. March 10 Monday • during class hours • close book • cheat sheet (one side of the printing paper) • Calculator is allowed. • MIPS register convention, instruction formats and operation code will be provided.

3. Two questions on Chapter 1

4. performanceX execution_timeY -------------------- = --------------------- = n performanceY execution_timeX Defining (Speed) Performance • To maximize performance, need to minimize execution time performanceX = 1 / execution_timeX If X is n times faster than Y, then • Decreasing response time almost always improves throughput

5. performanceAexecution_timeB 15 -------------------- = --------------------- = n ------ = 1.5 performanceB execution_timeA 10 Relative Performance Example • If computer A runs a program in 10 seconds and computer B runs the same program in 15 seconds, how much faster is A than B? We know that A is n times faster than B if The performance ratio is So A is 1.5 times faster than B

6. CPU Clocking • Operation of digital hardware governed by a constant-rate clock Clock period Clock (cycles) Data transferand computation Update state • Clock period: duration of a clock cycle • e.g., 250ps = 0.25ns = 250×10–12s • Clock frequency (rate): cycles per second • e.g., 4.0GHz = 4000MHz = 4.0×109Hz

7. Instruction Count and CPI • Instruction Count for a program • Determined by program, ISA and compiler • Average cycles per instruction • Determined by CPU hardware • If different instructions have different CPI • Average CPI affected by instruction mix

8. performanceA execution_timeB 600 x I ps ------------------- = --------------------- = ---------------- = 1.2 performanceB execution_timeA 500 x I ps Using the Performance Equation • Computers A and B implement the same ISA. Computer A has a clock cycle time of 250 ps and an effective CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and an effective CPI of 1.2 for the same program. Which computer is faster and by how much? Each computer executes the same number of instructions, I, so CPU timeA = I x 2.0 x 250 ps = 500 x I ps CPU timeB = I x 1.2 x 500 ps = 600 x I ps Clearly, A is faster … by the ratio of execution times

9. Amdahl’s Law • Improving an aspect of a computer and expecting a proportional improvement in overall performance • Example: multiply accounts for 80s/100s • How much improvement in multiply performance to get 5× overall? • Can’t be done! • Corollary: make the common case fast

10. Amdah’s Law, together with the CPU performance equation, is a handy tool for evaluation potential enhancements.

11. MIPS as a Performance Metric • MIPS: Millions of Instructions Per Second • Faster computers have a higher MIPS rating. • Doesn’t account for • Differences in ISAs between computers • Differences in complexity between instructions • We cannot compare computers with different instruction sets using MIPS.

12. 4 short questions regarding 2’s complement representation

13. Unsigned Binary Integers • The value of ith digit d is • d * Basei • i starts at 0 and increases from right to left • Example • 0000 0000 0000 0000 0000 0000 0000 10112= 0 + … + 1×23 + 0×22 +1×21 +1×20= 0 + … + 8 + 0 + 2 + 1 = 1110 • lease significant bit: the rightmost bit • most significant bit: the leftmost bit

14. Unsigned Binary Integers • Given an n-bit number • Using 32 bits • 0 to +4,294,967,295 • Range: 0 to +2n – 1 • These positive numbers are called unsigned numbers.

15. Hexadecimal • Base 16 • Compact representation of bit strings • 4 bits per hex digit • Example: eca8 6420 • 1110 1100 1010 1000 0110 0100 0010 0000

16. 2s-Complement Representation • Given an n-bit number • Example • 1111 1111 1111 1111 1111 1111 1111 11002= –1×231 + 1×230 + … + 1×22 +0×21 +0×20= –2,147,483,648 + 2,147,483,644 = –410 • Range: –2n – 1 to +2n – 1 – 1 • Using 32 bits • –2,147,483,648 to +2,147,483,647 • Most-negative: 1000 0000 … 0000 • Most-positive: 0111 1111 … 1111

17. 2s-Complement Signed Integers • Every computer today uses two’s complement binary representation for signed numbers. • Bit 31 is sign bit • 1 for negative numbers • 0 for non-negative numbers • 231 can’t be represented • Non-negative numbers have the same unsigned and 2s-complement representation • Some specific numbers • 0: 0000 0000 … 0000 • –1: 1111 1111 … 1111

18. Signed Negation • Complement and add 1 • Complement means 1 → 0, 0 → 1 • Example: negate +2 • +2 = 0000 0000 … 00102 • –2 = 1111 1111 … 11012 + 1 = 1111 1111 … 11102

19. complement all the bits 0101 1011 and add a 1 and add a 1 0110 1010 complement all the bits -23 = -(23 - 1) = 23 - 1 =

20. Sign Extension • Representing a number using more bits • Preserve the numeric value • In MIPS instruction set • lb, lh: extend signed loaded byte/halfword • Replicate the sign bit to the left • c.f. unsigned values: extend with 0s • Examples: 8-bit to 16-bit • +2: 0000 0010 => 0000 00000000 0010 • –2: 1111 1110 => 1111 11111111 1110

21. 1 - 2 short question(s) related to instruction format • R • I • J

22. Machine Language – Arithmetic Instruction

23. op rsrtrdshamtfunct MIPS Instruction Fields 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits • op • rs • rt • rd • shamt • funct opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions), 00000 for now function code that selects the specific variant of the operation specified in the opcode field (extends opcode)

24. op rs rt constant or address 6 bits 5 bits 5 bits 16 bits MIPS I-format Instructions • Immediate arithmetic and load/store instructions • rs: source register number • rt: destination register number • Constant: –215 to +215 – 1 • Address: offset added to base address in rs • Example: • addi $s1, $s2, 100 • 8 18 17 100

25. Design Principle 4: Good design demands good compromises • The similarity of the binary representations of related instructions simplifies hardware design. • Different formats complicate decoding, but allow 32-bit instructions uniformly • First three fields are the same in R-type and I-type • Formats are distinguished by the first field

26. 5 16 17 ???? 4 16 17 ???? op rsrt 16 bit number Assembling Branches • Instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 • Machine Formats: • How is the branch destination address specified? I format

27. Could specify the memory address - but that would require a 32 bit field Specifying Branch Destinations • Could use a “base” register and add to it the 16-bit offset • which register? • Instruction Address Register (PC = program counter) - its use is automatically implied by branch • PC gets updated (PC+4) during the Fetch cycle so that it holds the address of the next instruction • limits the branch distance to -215 to +215-1 instr’s from the (instruction after the) branch • but most branches are local anyway PC  bne $s0,$s1,Lbl1 add $s3,$s0,$s1 Lbl1: ...

28. op rsrt 16 bit offset Assembling Branches Example • Assembly code bne $s0, $s1, Lbl1 add $s3, $s0, $s1Lbl1: ... • Machine Format of bne: I format 5 16 17 0x0001 • Remember • After the bne instruction is fetched, the PC is updated so that it is addressing the add instruction (PC = PC + 4). • The offset (plus 2 low-order zeros) is sign-extended and added to the (updated) PC

29. 2 ???? Assembling Jumps • Instruction: j Lbl #go to Lbl • Machine Format: J format op 26-bit address • How is the jump destination address specified? • As an absolute address formed by • concatenating 00 as the 2 low-order bits to create a 28 bit address • concatenating the upper 4 bits of the current PC (now PC+4)

30. Target Addressing Example • Loop code from earlier example • Assume Loop at location 80000

31. 3-4 questions on assembly language programming • Convert from C/C++ to ASM • Given the assembly code, describe what it does • Best ways to study • Homework • Examples in lecture slides • Notes

32. Review: MIPS Instructions, so far

33. Review: MIPS Instructions, so far