CMPT 250 Computer Architecture

1. CMPT 250 Computer Architecture Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. State-Machine Diagrams contd.(Chapter 5, Section 5-7) • Use boolean expressions to simplify the diagram. Inputs: A, B Outputs: Y, Z Defaults: Y=0,Z=0 B/Y S0 Reset A AB A S3 S1 Z (A+B)/Y (A+B)/Z A B Y,Z A S2 AB B/Y

3. Input Conditions in State-Machine Diagrams • Input condition: boolean expression or equation in terms of input variables. • Transition condition (TC): an input condition on a transition arc, and causes a state transition to occur. • Unconditional transition: always occurs on the next clock. It can be thought of as having an implicit transition condition equal to 1.

4. Output Conditions in State-Machine Diagrams • Output condition (OC): an input condition that, if equal to 1, causes an output action to occur. • Moore output actions: unconditional for each state. • Transition-condition independent (TCI) Mealy output actions: depend on only states. • Transition-condition dependent (TCD) Mealy output actions: depend on both the state and a transition condition. • Transition and output condition dependent (TOCD) output actions: depend on the state, a transition condition, and an output condition. There is a slash between such an output action with its associated output condition.

5. Constraints on Input Conditions Inputs: A, B Outputs: Y, Z Defaults: Y=0,Z=0 AB A S Y,Z B The transition conditions from a given state Si must be mutually exclusive. An invalid example: The transition conditions from a given state must cover all possible combinations of input values.

6. Constraints on Output Conditions Z Inputs: A, B Outputs: Y, Z Defaults: Y=0,Z=0 AB A S Y,Z AB For every output action in state Si or on its transitions having coincident output variables with differing values, the corresponding pair of output conditions must be mutually exclusive. An invalid example: For every output variable, the output conditions for state Si or its transitions must cover all possible combinations of input values that can occur.

7. State-Machine Design of a Sliding Door Control

8. Sliding Door Control contd. • What states should we consider?

9. State-Machine Diagram for the Automatic Sliding Door BT Defaults: BT=0, CD=0, OD=0 LK, PA·PP·MO Closed LK·CL/CD Reset LK· (PA+PP+MO) OL Open OD OL PA+PP+MO Opened OL/OD PA·PP·MO PA+PP+MO+DR CL·PA·PP·MO·DR Close CD CL·PA·PP·MO·DR

10. Modified State Table for the Automatic Sliding Door

11. State Equations for the Automatic Sliding Door • PA + PP + MO appears frequently as factors in other transition conditions. • X = PA+PP+MO • Y1(t+1)=Y1·Y2·OL+Y1· Y2 +Y1·Y2·CL ·X·DR • Y2(t+1)=Y1·Y2·LK·X+Y1· Y2 +Y1·Y2·X+Y1·Y2·(X+DR)

12. Registers and Register Transfers(Chapter 7) • A register consists of a set of flip-flops, together with gates that implement their state transitions. • A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.

13. The Simplest Register • Consists of only flip-flops without external gates. D0 Q0 Clock D D Clear >C >C R R D1 Q1

14. Register with Parallel Load • Connect Load to C-input or D-input? Be careful of the clock skew. D0 Q0 Clock D Clear >C Load R C inputs Clock D1 Q1 D >C R

15. Register with Parallel Load contd. • Direct Load through gates into the D inputs. D0 Q0 D Load EN Clock >C EN D Q D D1 Q1 D Clock >C EN >C

16. Digital System Design • In most digital system designs, we partition the system into two types of modules: a datapath, and a controlunit. Control Signals Control Unit Data Path Control inputs Status Signals Data outputs Control outputs Data inputs

17. Register Transfer Operations • The registers are assumed to be basic components of the digital system. The movement of the data stored in registers and the processing performed on the data are referred to as register transfer operations. They are specified by the following three basic components. • The set of registers in the system. • The operations that are performed on the data stored in the registers, and • The control that supervises the sequence of operations in the system.

18. Register Transfer Operations contd. • Representations of Registers: R 7 6 5 4 3 2 1 0 (a) Register R (b) Bits of a register 15 0 15 8 7 0 R2 PC(H) PC(L) (c) A 16-bit Register (b) Bits of a register

19. Basic Symbols for Register Transfers

20. An Register Transfer Example • Transfer from R1 to R2 when K1 = 1. K1 Load R1 R2 n Clock

21. Microoperations • Transfer microoperations, which transfer binary data from one register to another. • Arithmetic microoperations, which perform arithmetic on data in registers. • Logic microoperations, which perform bit manipulation on data in registers. • Shift microoperations, which shift data in registers.

22. Shift Registers • A register capable of shifting its stored bits laterally in one or both directions is called a shift register. Serial input SI Serial output SO D D D D >C >C >C >C Clock

23. Ripple Counter • The flip-flop is positive edge triggered. D D D D D D D D >C >C >C >C >C >C >C >C R R R R R R R R Clock Reset

24. Multiplexer and Bus-based Transfers for Multiple Registers Enable R0 R0 select 2 EN 3-to-1 MUX R1 R1 bus EN R2 R2 EN Multiplexer Bus Three-state Bus

25. Control of Register Transfers • Programmable system: a portion of the input to the processor consists of a sequence of instructions. Each instruction specifies the operation that the system is to perform, which operands to use, where to place the results of the operation, and in some cases, which instruction to execute next. • Non-programmable system: the control unit determines the operations to be performed and the sequence of those operations, based on its inputs and the status bits from the datapath.

26. Register-Transfer System Design Procedure • Write a detailed system specification. • Define all external data and control input signals, all external data, control and status output signals, and the registers of the datapath and control unit. • Find a state machine diagram for the system including the register transfers in the datapath and in the control unit.

27. Register-Transfer System Design Procedure contd. • Define internal control and status signals. • Draw a block diagram of the datapath, and a block diagram of the control unit if it includes register transfer hardware. • Design any specialized register transfer logic in both the control and datapath. • Design the control unit logic. • Verify the design.

28. An Example: DashWatch • The DashWatch is a very inexpensive stopwatch. It has a 4-digit BCD counter called TM, and a 16-bit parallel load register SD. START Display Time STOP CSS RESET

29. Inputs, Outputs, and Registers of the DashWatch

30. State-Machine Diagram for the DashWatch RESET S1 SD<-(9999)BCD START S2 TM<-(0000)BCD START CSS·START STOP S3 TM<-(TM+1)BCD, DIS=TM STOP S4 CSS·START DIS=TM CSS S5 TM<SD TM>=SD START S7 S6 SD<-TM DIS=SD START

31. Datapath Output Actions and Status Generation

32. Datapath Block Diagram TM C0 ENTM 4-Digit BCD Counter RSTM SRST A<B Comparator ALTB DS D1 D0 S 16-Bit 2-to-1 MUX SD DIS LSR LOAD Storage Register 4-Digit BCD-to-7 RESET RESET D Segment Converter 16-Bit 2-to-1 MUX UPDATE 4-Digit LCD Display D1 D0 1 DP 1001100110011001

33. Control State-Machine Diagram Defaults: All outputs = 0 RESET S1 LSR START S2 RSTM START CSS·START STOP S3 ENTM STOP S4 CSS·START CSS S5 ALTB START S7 S6 UPDATE, LSR DS START

34. Thanks!