1 / 21

CMPT 250 Computer Architecture

CMPT 250 Computer Architecture. Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM. CISC Architecture.

arwen
Télécharger la présentation

CMPT 250 Computer Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. CMPT 250 Computer Architecture Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

  2. Design strategy in ASM

  3. CISC Architecture • The goal of the CISC architecture is to match more closely the operations used in programming language and to provide instructions that facilitate compact programs and conserve memory. • A purely CISC architecture has the following properties: • Memory access is directly available to most types of instructions. • Addressing modes are substantial in number. • Instruction formats are of different lengths. • Instructions perform both elementary and complex operations.

  4. Combined CISC-RISC Organization Instruction fetch Microprogram counter Decode and operand fetch Control ROM Execute Write-back

  5. CISC CPU Instruction Formats 31 25 24 20 19 15 14 10 9 0 Three register type OPCODE DR SA SB Two register type OPCODE DR SA Immediate Branch 1 OPCODE DR SA Large target offset Branch 2 OPCODE DR SA SB Short target offset

  6. Micro-programmed Control SA CA CA-1 MS MI +1 MZ 0 1 2 3 Mux E ME MZ-1 MC PS Z Address Microcode ROM Data MZ CA DOF EX MZ-1 CA-1

  7. Address Control

  8. Load Indirect Indexed(LII)

  9. A Personal Computer Screen Hard drive Keyboard Drive Controller Bus Interface Graphics Adapter RAM Processor CPU, FPU, MMU Internal Cache External Cache

  10. Access Times • Cache: 1 ns, memory: 10 ns, hard drive: 13 ms • Assume that 95% of the fetches will be from a cache and about 4.999995 percent of the fetches will be from main memory. The average access time then is: • 0.95*2+0.49999995*10+5*10-8*1.3*107=3.05ns

  11. Locality of Reference • Temporal Locality: refers to the relative times at which instructions and operands are accessed. • Spatial Locality: refers to the relative locations at which they reside in main memory.

  12. Write Methods • Write the result into main memory. This is also called write-through. • Write the result into the cache if there is a cache hit. This is also called write-back. • write-allocate: when a cache miss happens, read the line containing the word to be written from main memory into the cache, with the new word written into both the cache and main memory. Dirty bit of a line.

  13. THANKS!

More Related