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Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology

Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25  m Transistors. Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology April 21, 2005. Motivation.

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Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology

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  1. Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25 m Transistors Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology April 21, 2005

  2. Motivation • Enable the Microelectronic Engineering department to continue the semiconductor industry trend of fabricating high performance transistors that have faster switching speeds, increased density and functionality, and ultimately a decrease in cost per function. • Push the limits of the SMFL in all areas from design to fabrication to test • Create a baseline process that can be used to integrate strained silicon, metal gates, high-k gate dielectrics, and replacement gate technologies at RIT 2

  3. Outline • RIT/Industry Scaling Trends • Gate Control Fundamentals • Short Channel Effects • Deep-Submicron Scaling • Unit Process Development • Layout • Integration/Fabrication/Test • Time Line • Questions 3

  4. RIT/Industry Scaling Trends Table 1: RIT/Industry Scaling Trends [3] • Over last 30 years, transistors have gotten smaller and faster • 110x reduction in gate length • 36,000x increase in switching speed • Integrated circuits have become much more complex • 54,000x increase in number of transistors on an IC 4

  5. RIT/Industry Scaling Trends Table 1: RIT/Industry Scaling Trends [3] • In May of 2004 an NMOS transistor with LPOLY = 0.5 µm was developed • This is RIT’s smallest transistor with LEFFECTIVE = 0.4 µm • This is the same technology as the Intel Pentium from 9 years earlier 5

  6. RIT/Industry Scaling Trends Table 1: RIT/Industry Scaling Trends [3] • By September of 2005, this process will yield CMOS transistors • with LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm • This technology was used in high volume manufacturing of the Intel • Pentium III at 600 MHz only 6 years ago • The gap between industry and RIT is rapidly shrinking 6

  7. Outline • RIT/Industry Scaling Trends • Gate Control Fundamentals • Short Channel Effects • Deep-Submicron Scaling • Unit Process Development • Layout • Integration/Fabrication/Test • Time Line • Questions 7

  8. Gate Control Fundamentals • NMOS Transistor • 4 Terminal Device • Gate • Source • Drain • Body • To turn transistor on: • Apply positive charge to Gate, QG • A depletion region in the p-type body is created as positively • charged holes are repelled by gate, exposing negatively charged • acceptor ions, QB • As the gate charge is further increased, electrons from the source • diffuse into the channel and become inversion charge, QI • QG = QB + QI Figure 1: Schematic of NMOS Transistor [4] 8

  9. Gate Control Fundamentals • The source and body • terminals are grounded • A positive voltage is • applied to the drain, VDS • Inversion charge moves • from source to drain and • is the current in the device Figure 1: Schematic of NMOS Transistor [4] • Equation 1 shows the classical derivation for drain current in a • transistor by integrating the inversion charge along the channel (Eq. 1) 9

  10. Gate Control Fundamentals • A depletion region from • the drain is created by the • reverse biased body-drain • p-n+ diode • The positively charged • donor ions in drain support • some of the negative • inversion charge • This is known as “Charge Sharing” as the gate does not have full • control over the inversion channel • For large gate lengths, the contribution of the drain in controlling • the inversion layer is small compared to the gate contribution • As transistors are scaled smaller in gate length, the drain has a • larger percentage contribution in supporting inversion charge in • the channel Figure 1: Schematic of NMOS Transistor [4] 10

  11. Outline • RIT/Industry Scaling Trends • Gate Control Fundamentals • Short Channel Effects • Deep-Submicron Scaling • Unit Process Development • Layout • Integration/Fabrication/Test • Time Line • Questions 11

  12. Short Channel Effects • “Gate Control” is the most important concept in scaling of transistors • The consequence of the drain taking control away from the gate • is short channel effects such as: • VT Roll-off • Drain Induced Barrier Lowering (DIBL) • Punch-through • Threshold voltage decreases • as gate length decreases • For small enough gate lengths • the devices will be on at 0 V Figure 2 : VT Roll-off Effect [1] 12

  13. Short Channel Effects • “Gate Control” is the most important concept in scaling of transistors • The consequence of the drain taking control away from the gate • is short channel effects such as: • VT Roll-off • Drain Induced Barrier Lowering (DIBL) • Punch-through • Increased off-state leakage with • increase in drain voltage • If gate were in full control, these • curves would be one on top of the • other Figure 3: Drain Induced Barrier Lowering (DIBL) [1] 13

  14. Short Channel Effects • “Gate Control” is the most important concept in scaling of transistors • The consequence of the drain taking control away from the gate • is short channel effects such as: • VT Roll-off • Drain Induced Barrier Lowering (DIBL) • Punch-through • At high drain bias, the drain • takes control of current • through the device • Excessive heating can occur • and cause device failure Figure 4: Lateral source/drain Punch-through [4] 14

  15. Short Channel Effects • “Gate Control” is the most important concept in scaling of transistors • The consequence of the drain taking control away from the gate • is short channel effects (SCE) such as: • VT Roll-off • Drain Induced Barrier Lowering (DIBL) • Punch-through • Transistors with short channel effects are undesirable • These SCE must be minimized to yield long-channel transistors 15

  16. Outline • RIT/Industry Scaling Trends • Gate Control Fundamentals • Short Channel Effects • Deep-Submicron Scaling • Unit Process Development • Layout • Integration/Fabrication/Test • Time Line • Questions 16

  17. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Figure 5: Physical Scaling Guidelines [7] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters 17

  18. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Figure 5: Physical Scaling Guidelines [7] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • Decrease gate oxide thickness • Gate is closer to the channel • More control in switching device off • Cox since Cox = A/tox or Cox =Q/V • ID and gm since  Cox 18

  19. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Figure 5: Physical Scaling Guidelines [7] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • Decrease junction depth of source/drain • Depletion region from gate dominates • depletion region from the drain • Trade-off is sheet resistance  and ID  • ND must  which will cause RS 19

  20. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Figure 5: Physical Scaling Guidelines [7] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • Use sidewall spacer to create deeper • source/drain junction called the contact • Typically ~2x as deep as shallow LDD • Doped heavily to reduce RS 20

  21. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Figure 5: Physical Scaling Guidelines [7] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • Increase doping of channel to decrease • the depletion region from the source/drain • Use a retrograde profile where doping is • low at the surface and higher sub-surface • Mobility of carriers  • ID and gm since both are  mobility 21

  22. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • As TOX, gate leakage current  • VDD must  to reduce this leakage • VT must  so (VGS-VT) , this is “Gate Overdrive” and is  ID • Want ION  since gate delay  ION-1 22

  23. Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6] Deep-Submicron Scaling • The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters • Want IOFF to be low to reduce standby power • The industry standard metric is 1 nA/µm of off-current • This results in 5.75 decades between ION and IOFF • There is 500 mV swing between 0 V and VT • SS of 85 mV/decade is needed to turn the device off Theoretical limit ~ 60 mV/decade @ 300K 23

  24. Outline • RIT/Industry Scaling Trends • Gate Control Fundamentals • Short Channel Effects • Deep-Submicron Scaling • Unit Process Development • Layout • Integration/Fabrication/Test • Time Line • Questions 24

  25. Super Steep Retrograde Twin Well • Nitride Sidewall Spacers • Rapid Thermal Dopant Activation • 2 Level Aluminum Metallization • Back End CMP • Shallow Trench Isolation • Dual Doped Poly Gates • 50 Å gate oxide w/ N2O • Low Doped Source/Drain Extensions • Titanium Silicide 0.25 µm Device Technology • Unit Processes will be developed to yield cross-section shown in Figure 6 Figure 6: CMOS Cross Section showing NMOS (left) and PMOS (right) Transistors 25

  26. Unit Process Development • Shallow Trench Isolation • Channel Engineering • Uniformly Doped Twin Well • Super Steep Retrograde Well • Ultra Thin Gate Oxide • Gate Formation • Lithography • Resist Trimming • Reactive Ion Etch (RIE) of Gate • Source/Drain/Gate Doping • Poly re-ox • Low Doped Source/Drain Extensions • Sidewall Spacers • Source/Drain Contacts • Dual Doped Poly • Rapid Thermal Dopant Activation • Titanium Salicide • Contact Cut Etch • 2 Level Aluminum Metallization Figure 7: Shallow Trench Isolation 26

  27. Shallow Trench Isolation • Replacement of LOCOS as preferred isolation technology • LOCOS suffers from “Bird’s Beak” effect • Field oxide encroaches into active region, reducing W • Reduction in Width leads to reduction in drive current • To recover this loss, transistors must be made wider • which takes up more real estate • Small geometries are not possible since Bird’s Beak • oxide encroaches from both sides of active area • With STI, WACTUAL ≈ WDRAWN • Increased packing density • Higher drive current for devices with same WDRAWN • Decreased topography early in the process 27

  28. Shallow Trench Isolation • Grow Pad Oxide • Deposit Nitride by LPCVD • Pattern and Etch Silicon Trench • Grow liner oxide to repair silicon • and round off sharp corners • Fill with PECVD TEOS Oxide • CMP trench oxide • Use Nitride as etch stop • Remove Nitride in H3PO4 acid Figure 8: STI Process after trench etch Figure 9: STI Process after trench fill Figure 10: STI Process after CMP 28

  29. Unit Process Development • Shallow Trench Isolation • Channel Engineering • Uniformly Doped Twin Well • Super Steep Retrograde Well • Ultra Thin Gate Oxide • Gate Formation • Lithography • Resist Trimming • Reactive Ion Etch (RIE) of Gate • Source/Drain/Gate Doping • Poly re-ox • Low Doped Source/Drain Extensions • Sidewall Spacers • Source/Drain Contacts • Dual Doped Poly • Rapid Thermal Dopant Activation • Titanium Salicide • Contact Cut Etch • 2 Level Aluminum Metallization 29

  30. Channel Engineering Figure 11: Uniformly Doped Twin Wells Figure 12: Super Steep Retrograde Wells • Uniformly Doped Twin Wells • NMOS built in p-well • PMOS built in n-well • Set Field VT to stop parasitic • conduction channels from • forming between adjacent • devices • Super Steep Retrograde Wells • 2nd step in well formation process • Lower doping at surface which • transitions to higher doping • sub-surface • Control short channel effects • Set active VT 30

  31. Uniformly Doped Twin Well • In industry, wells are implanted through • the trench oxide with energies of 1 MeV • to place the peak 1 µm below the surface • The limit of the Varian 350D Ion Implanter • is 190 KeV which is not high enough to • implant through 3000 Å of trench oxide • Also, there will be non-uniformities in silicon trench depth and • TEOS oxide fill. • For packing density purposes, multiple active regions are built in the same well with 1 common contact • It is therefore required for the well doping to be continuous under the trench oxide regions • For this process, the wells will be implanted before the trench oxide • fill in the STI process to ensure the wells are continuous in the field Figure 11: Uniformly Doped Twin Wells 31

  32. Uniformly Doped Twin Well Table 3: Field Region VT Figure 11: Uniformly Doped Twin Wells • A drive-in thermal step will create uniform wells with: • ND = 1x1017 cm-3 • XJ-WELL = 1 µm • With a 2.0 V supply, the field-VT is sufficiently large • The junction depth of the wells must be large enough to prevent • vertical punch-through between the reverse-biased drain and • complimentary doped starting wafer • A junction depth of 1 µm will provide more than enough tolerance 32

  33. Super Steep Retrograde Well Figure 12: Super Steep Retrograde Wells • Increased carrier mobility due to lower channel doping at surface • Increased drive current due to increased mobility • Suppression of short channel effects (SCE) such as VT roll-off, punch- • through, and drain induced barrier lowering (DIBL) due to the higher • peek doping sub-surface • Latch-up is suppressed because the base regions of parasitic BJTs are • doped higher, therefore reducing their gain. 33

  34. Super Steep Retrograde Well Figure 12: Super Steep Retrograde Wells • Increased carrier mobility due to lower channel doping at surface • Increased drive current due to increased mobility • Suppression of short channel effects (SCE) such as VT roll-off, punch- • through, and drain induced barrier lowering (DIBL) due to the higher • peek doping sub-surface • Latch-up is suppressed because the base regions of parasitic BJTs are • doped higher, therefore reducing their gain. 34

  35. Super Steep Retrograde Well Peak channel concentration Lower surface doping concentration Uniform well for Field VT Figure 13: Super Steep Retrograde Profile [10] • Implanted after uniformly doped wells go through drive-in • In Industry, heavy ions that are slow diffusers are used: • Indium (In) is used for p-well of NMOS • Antimony (Sb) or Arsenic (As) are used for n-well of PMOS • At RIT, Boron and Phosphorous are available • Boron (B) will be used for p-well of NMOS • Phosphorous (P) will be used for n-well of PMOS • Are more susceptible to transient enhanced diffusion (TED) • Won’t produce profiles as steep as In or Sb but by keeping • thermal budget low, can still produce retrograde profiles 35

  36. Unit Process Development • Shallow Trench Isolation • Channel Engineering • Uniformly Doped Twin Well • Super Steep Retrograde Well • Ultra Thin Gate Oxide • Gate Formation • Lithography • Resist Trimming • Reactive Ion Etch (RIE) of Gate • Source/Drain/Gate Doping • Poly re-ox • Low Doped Source/Drain Extensions • Sidewall Spacers • Source/Drain Contacts • Dual Doped Poly • Rapid Thermal Dopant Activation • Titanium Salicide • Contact Cut Etch • 2 Level Aluminum Metallization 36

  37. 50 Å Gate SiO2 with N2O Incorporation Figure 14: Ultra Thin Gate Oxide • NTRS Roadmap suggests 40 – 50 Å, target for this process is 50 Å • ox = 4 MV/cm, this is at limit of Fowler-Nordheim tunneling • Nitrogen is incorporated into oxide to block diffusion of boron from • p+ poly gate into channel of PMOS transistor • Surface Charge Analysis can be done to determine density of interface • trap states. 37

  38. Unit Process Development • Shallow Trench Isolation • Channel Engineering • Uniformly Doped Twin Well • Super Steep Retrograde Well • Ultra Thin Gate Oxide • Gate Formation • Lithography • Resist Trimming • Reactive Ion Etch (RIE) of Gate • Source/Drain/Gate Doping • Poly re-ox • Low Doped Source/Drain Extensions • Sidewall Spacers • Source/Drain Contacts • Dual Doped Poly • Rapid Thermal Dopant Activation • Titanium Salicide • Contact Cut Etch • 2 Level Aluminum Metallization Figure 15: Poly Gate Formation 38

  39. Gate Formation - Lithography Figure 16: ASML DUV Stepper Figure 17: Canon i-line Stepper • Canon FPA-2000i1 stepper • 365 nm i-line source • Capable of 0.5 µm lines/spaces • Standard resist coat/develop track • Capable of 0.05 µm overlay error • ASML PAS 5500/90 stepper • 248 nm KrF excimer laser • Capable of 0.25 µm lines/spaces • Tool is currently down, laser 39

  40. Gate Formation – Resist Trimming Figure 18: Resist Trimming Process • Resist trimming can be used to make 0.5 µm line a 0.25 µm line for gate • Isotropically etch 1250 Å of resist of sides and top of 0.5 µm line • Resist thickness reduced from 10,000 Å to 8750 Å • This is still sufficiently thick to protect poly during gate plasma etch • Line width reduced to 0.25 µm target in photoresist • This technique will be explored if over-exposing/developing is not successful 40

  41. Gate Formation – RIE Poly • Polysilicon thickness is reduced for smaller gate lengths • 2500 Å target will provide 1:1 aspect ratio for plasma etch • Will block up to 50 keV Phosphorous and 30 keV Boron • Want high selectivity of poly to oxide since oxide is very thin • Reactive Ion Etcher will be used since it etches anisotropically • Etch rate is higher in the vertical direction compared to horizontal • If etch was isotropic, enough under-cut would occur due to lateral • etching that 0.25 µm would be etched away and remove the • photoresist masking layer Figure 19: Under-Cut of Gate Mask 41

  42. Unit Process Development • Shallow Trench Isolation • Channel Engineering • Uniformly Doped Twin Well • Super Steep Retrograde Well • Ultra Thin Gate Oxide • Gate Formation • Lithography • Resist Trimming • Reactive Ion Etch (RIE) of Gate • Source/Drain/Gate Doping • Poly re-ox • Low Doped Source/Drain Extensions • Sidewall Spacers • Source/Drain Contacts • Dual Doped Poly • Rapid Thermal Dopant Activation • Titanium Salicide • Contact Cut Etch • 2 Level Aluminum Metallization 42

  43. Poly Re-Oxidation • After plasma etch of gate there is damage to edges of gate oxide • A 250 Å oxide will be thermally grown to: • Repair damage to gate oxide from • plasma etch of the poly gate • Create a thicker screening oxide for • source/drain extension implant • Make a thicker etch stop for sidewall • spacer etch process • Form an off-set region for lateral diffusion of shallow s/d extension • Want to reduce gate overlap of s/d to reduce Miller Capacitance • This capacitance will reduce the cut-off frequency of the device • Need 15 – 20 nm overlap or drive current will degrade [11] Figure 20: Poly Re-Oxidation 43

  44. LPOLY = 250 nm XJ = 75 nm 52.5 nm 52.5 nm LEFFECTIVE = 180 nm Poly Re-Oxidation Figure 21: Gate Overlap and LEFFECTIVE Calculation • Gate Overlap = 52.5 nm – 25 nm = 27.5 nm ≥ 15 – 20 nm requirement • Process is designed for LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm 44

  45. Low Doped Source/Drain Extensions • Shallow junctions implanted after • poly re-ox step • A portion of VDS is dropped across • the LDD so a lower effective voltage • is across the channel (Eq. 2) • The advantage of this is reduced • hot carrier effects since carriers see lower horizontal electric field • The trade-off is there will be a reduction in drive current & switching speed Figure 22: Low Doped Source/Drain Extensions Figure 23: Equivalent Circuit with Parasitic Resistance Vchannel = VDS – 2*IDS(Rterminal + Rs/d + RLDD) (Eq. 2) 45

  46. Low Doped Source/Drain Extensions Table 4: NTRS Guidelines for LDD Scaling [6] • Low end of range is chosen for XJ and RS so if more diffusion • occurs then is anticipated, the devices will still operate properly • The implant energy must be selected to place the peak of the • implant at the Silicon surface. With a 300 Å screening oxide layer: • B11 of 10 keV • P31 of 25 keV • The Varian 350D is capable of implant energies as low as 10 keV • In industry, Silicon (Si) or Germanium (Ge) are implanted before • the shallow S/D implants to reduce channeling of dopant ions 46

  47. Silicon Nitride Sidewall Spacers Figure 24: Nitride Sidewall Spacers Figure 25: SEM Micrograph of Nitride Spacer • Sidewall spacers are formed after the LDD implants to create an • offset region where a deeper source/drain contact region can be • implanted. Figure 26: Sidewall Spacer Process 47

  48. VDD = 2.0 V |VT| = 0.5 V Tox = 50 Å = 4108 µm Silicon Nitride Sidewall Spacers • In a perfectly anisotropic etch the Lspacer = tpoly = 0.25 µm • Parasitic LDD resistance is controlled by length of sidewall spacer (Eq. 3) (Eq. 4) Table 5: Sidewall Spacer Length Effect on Drive Current [9] • NTRS Guidelines require < 10% reduction in drive current due • to parasitic source/drain extension resistance • Source/Drain contact resistance must also be taken into account 48

  49. Source/Drain Contact • Source/Drain contacts implanted after sidewall spacer formation • and are self-aligned to the gate Figure 27: Source/Drain Contact and Gate Doping • Contact is doped higher and junction depth deeper to • decrease parasitic source/drain resistance • Silicide thickness must account for < ½ contact junction depth • or increased leakage current will result 49

  50. Source/Drain Contact Table 6: NTRS Guidelines for Source/Drain Contact Scaling [6] • Midpoint of XJ range chosen so XJ-CONTACT ~ 2*XJ-LDD • The implant energy must be ~ 2x higher then shallow LDD implants: • B11 of 20 - 30 keV • P31 of 40 - 50 keV • The sheet resistance of this region must be decreased to decrease • the reduction in drive current • The polysilicon gates are doped n+ for NMOS and p+ for PMOS at • the same time the contacts are doped. 50

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