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Problem 6 ESD Current Path

Problem 6 ESD Current Path. Speaker: Chuang-Chi Chiou Advisor: Chun-Yao Wang 2005/05/11. Input. .SUBCKT test A B VCC VCC3A GND MM2 15 A GND 9 NG MM4 15 A VCC VCC PG MM5 20 15 GND GND NG MM6 VCC3A 8 9 9 NG

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Problem 6 ESD Current Path

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  1. Problem 6 ESD Current Path Speaker: Chuang-Chi Chiou Advisor: Chun-Yao Wang 2005/05/11

  2. Input .SUBCKT test A B VCC VCC3A GND MM2 15 A GND 9 NG MM4 15 A VCC VCC PG MM5 20 15 GND GND NG MM6 VCC3A 8 9 9 NG MM7 B 20 8 9 NG RR1 20 VCC RS DD0 GND 15 DP .ENDS

  3. Process • Read File • Bucket Sort • Add Connection • Group • Find Paths

  4. Bucket Sort • Purpose • Because node name is string, we need some faster approach to transfer node name to it’s array index • Approach • Sum each character (ASCII) then mod bucket size VCC = (86 + 67 + 67) mod bucket_size 15 = (49 + 53) mod bucket_size

  5. Read File • .SUBCKT test A B VCC VCC3A GND • circuit name: test • Pin: A, B, VCC, VCC3A, GND • MM2 15 A GND 9 NG • Add bi-direction connection 15 GND (drain source) • Add uni-direction connection A 15 (gate) • Add uni-direction connection A GND (gate) • DD0 GND 15 DP • Add bi-direction connection GND 15 (drain source) • RR1 20 VCC RS • Add bi-direction connection 20 VCC (drain source)

  6. Group • Group: nodes which are connected by source-drain path • Start from each pin • Use DFS (Depth First Search) • Signal should die outfrom one pin to another one

  7. Group Find (VCC,GND) VCC 20 B A 15 8 GND 9 VCC3A

  8. Group VCC 15 20 B 8 A GND 15 20 VCC3A 9

  9. Path • (VCC,GND) • (A,VCC) • (A,GND) • (VCC,B) • (GND,B) • (B,VCC3A)

  10. Hierarchical sub-circuit • Record sub-circuit name, path (including number of gates this path passed) • Add connection according to path information

  11. Hierarchical sub-circuit .SUBCKT CC 1 2 MM1 1 2 1 8 NG .ENDS .SUBCKT DD 44 47 X11652 47 44 CC .ENDS .SUBCKT TEST2 AA BB VCC3IK GNDIK MM2 114 AA GNDIK 9 NG MM4 114 AA VCC3IK VCC3IK PG X156 114 VCC3IK_PLL DD MM8 EE AA BB VCC3IK PG .ENDS (1,2) gate (44,47) gate Add connection 114,VCC3IK_PLL (gate)

  12. Sub-circuit definition .SUBCKT TEST2 AA BB VCC3IK GNDIK MM2 114 AA GNDIK 9 NG MM4 114 AA VCC3IK VCC3IK PG X156 114 VCC3IK_PLL DD MM8 EE AA BB VCC3IK PG .ENDS .SUBCKT DD 44 47 X11652 47 44 CC .ENDS .SUBCKT CC 1 2 MM1 1 2 1 8 NG .ENDS main Add connection 114,VCC3IK_PLL (gate) main main P1 P1 (44,47) gate P2 (1,2) gate

  13. CPU Time

  14. Memory Usage

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