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Particles and Fields Package Pre-Environmental Review May 22 -23, 2012 17 - PFDPU

Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission. Particles and Fields Package Pre-Environmental Review May 22 -23, 2012 17 - PFDPU D. Gordon / W. Donakowski PFDPU Team. Introduction. Overview. Electrical Components covered in this presentation: DCB REG IIB

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Particles and Fields Package Pre-Environmental Review May 22 -23, 2012 17 - PFDPU

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  1. Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission Particles and Fields Package Pre-Environmental Review May 22 -23, 2012 17 - PFDPU D. Gordon / W. Donakowski PFDPU Team

  2. Introduction

  3. Overview Electrical Components covered in this presentation: DCB REG IIB Remaining PFDPU resident boards are covered by the Instrument specific presentations. Mechanical presentation covers the entire PFDPU Vibration and Thermal Vacuum Procedures performed on the entire PFDPU

  4. PFDPU Hardware Team DCB (Processor) Dorothy Gordon REG (Power Supplies, Switches and Actuator Control) – Peter Berg and Dennis Seitz IIB (Instrument Power Regulators and Signal Distribution) Chris Tiu Mechanical William Donakowski QA and Manufacturing Jorg Fischer Chris Scholz William Whitehead (visiting, R&QA) Mike Raffanti PFDPU Resident Instrument Boards SEP/DAP Team (SSL) DFB/BEB Team (LASP) MAG Team (GSFC)

  5. Electrical Block Diagram IIB not shown, sits between LVPS(REG)/DCB and the Instruments REG1 REG2 DCB1 DCB2

  6. Relevant Documentation MAVEN_PF_SYS_004 – PFDPU to Instruments ICD MAVEN_PF_SYS_003 – Power Converter Requirements MAVEN_PF_PFDPU_001 – Data Controller Board Specification MAVEN_PF_SYS_021_PowerDistribution MAVEN_PF_SYS_014_Grounding MAVEN_PF_SYS_013 – Harnessing Drawing MAVEN_PF_SYS_016 – Connector Pinouts MAV-IDP-MEC-002 MAVEN PFDPU MAV-IDP-MEC-020 DAP Assy MAV-IDP-MEC-022 IIB Assy MAV-IDP-MEC-026 REG Assy MAV-IDP-MEC--028 DCB Assy Schematics & PCB Layouts (REG, IIB, DCB, FPGA Daughter Board) MAVEN_PF_TP_046_PFP_FM_Integration&Test MAVEN_PF_TP_042_REV A PFDPU_Vibration_Test Procedure MAVEN_PF_TP_044_PFDPU_Thermal_Vac_Test MAVEN_PF_TP_031_PFDPU_CPT MAVEN_PF_TP_045_PFDPU_LPT

  7. Status/Test Results - DCB DCB and FPGA Daughter Board Both Flight Boards have been received and have passed board level test MAVEN_PF_PFDPU_DCB_600C_TESTPLAN Initial test using prototype FPGA daughter board Final test/characterization using flight FPGA daughter board Cleaning/Conformal Coat and final assembly completed Following board level recheck, ready for PFDPU Integration FPGA Final flight port completed as of 28 FEB 2012 Static Timing Analysis predicts 21 MHz operation over temperature/radiation environment (FPGA SCLK = 16.8MHz) Flattenned/backannotated simulation verification All realtime tests successful

  8. DCB and FPGA Daughter Board

  9. DCB Current Measurements Actual current drain is somewhat less than predicted (FPGA Designs tools have tended to give pessimistic estimates). Draw on analog supplies has been reduced by keeping the ADC in standby mode most of the time. Stability of supplies has been verified with REG board. Power turnon profiles of FPGA supplies verified with REG/DCB boards (stable within 5 ms, 1.5V supply on prior to 3.3V supply crossing to a logic “high”).

  10. Status/Test Results - REG REG FM1

  11. REG Test/Qualification • Tests in process for FM1 and FM2: • System clock sync • Main converter inrush current • Output switches function • Output voltage regulation and ripple over output load and input voltage ranges • Efficiency versus input power • Main transformer waveforms • Current and voltage monitor calibrations • Output over-current sense function • On board thermometer • Actuator section inrush current • Actuator function • Actuator dead man timer function • Status: • Improved resistor is required for the Current Monitor (IMON) circuit • Awaiting Flight parts (Vishays) (due 5/14) • Soft start modification/test underway

  12. IIB Flight IIB

  13. IIB Test/Qualification/Status • Flight board tests completed: • Parts installation inspection Connector pin-to-pin measurements Tantalum capacitor power-on polarity Power converter waveforms Output voltage regulation Output voltage ripple Input current ripple Power efficiency Measured Efficiencies LPW Half load:  73.7% Full load:  77.8% SEP Half load:  73.7% Full load:  78.6% MAG1 Half load:  62.6% Full load:  70.1% MAG2 Half load:  61.2% Full load:  70.6% • Status: • Cleaning completed • Conformal Coat scheduled for week of 14 MAY 12

  14. PFDPU CPT and LPT Comprehensive and Limited Test Plans Exercise the DCB and REG (and the IIB as needed) Focus on subsystems not covered by the Instrument CPTs Flexible configuration Can be run with any number of instruments integrated Option to perform MAG Heater Control and Actuator Subsystem checkouts Can be performed with GSE or Instrument Hardware Analog Housekeeping logged to facilitate trending Most test executions run at 28V IN to allow comparisons between various results CPT One hour test per instrument Goal: run the CPT for the entire suite within 1 day Tests both sections of the PFDPU (redundant DCB/REG) and both S/C Interfaces (redundant A/B sides) LPT Reduced version of CPT (runs in about 10 minutes) Goal: run the LPT for the entire suite in about 1 hour Operates on one section of PFDPU and one S/C Side (configurable per test)

  15. PFDPU Integration and Test Flow

  16. PFDPU PFRs The majority relate to manufacturing issues, minor layout or parts tuning Most require minor rework, for some the disposition is to “leave as-is” Solutions are implemented, we are awaiting final sign-off PFR_052 (REG) involves damage requiring parts replacement FRB held Analysis identified damaged or stressed parts All damaged and stressed parts replaced and re-tested Ready to close

  17. Requirements Validation (FRD and ERD Based) FRD Based ERD Based

  18. Requirements Validation (ICD Based) Snapshot of PFDPU Requirements (First 6 out of 25 PFDPU Related Requirements shown above). Excerpted from MAVEN_PF_SYS_033B_VerificationMatrix Most items verify the S/C to PFDPU Interface (both functional and low level hardware) Some items are tested/verified with the FM I & T Procedure; others will require dedicated test reports. Some functional tests are generic and can be performed on the ETU with results extrapolated to Flight.

  19. MAVEN PFDPU Particle and Fields Data Processing Unit Bill Donakowski UCB/SSL Mechanical Engineer billd@ssl.berkeley.edu

  20. PFDPU Overview • 11 Individual Cards Bolted Together • Open Frames, 6061 T6 Al • Separate S/C Attach Bracket • Bolted to S/C via 6 X 8-32 bolts • Thermally coupled to S/C • Electrically grounded to S/C • Ground Straps • Straps provided by L-M • Black anodized exterior surfaces • No Thermal Blankets • Mass CBE 7 Kg

  21. PFDPU STATUS and SCHEDULE Analysis (FEM Dynamics/Steinberg) Completed Box Structural Enhancements Incorporated Flight Hardware Status UCB Flight Hardware Build nearly complete (SEP/REG/DCB/IIB) LASP hardware (BEB/DFB) delivery imminent GSFC hardware (MAG, ACHE) delivery imminent Card Electrical Check-out May/June 2012 Complete PFDPU Build-Up July 2012 Vibration Testing August 2012 TVAC Testing August - September 2012 (UCB/SSL)

  22. Structural Dynamics Analysis Steinberg Fatigue Life Analysis/FEM Analysis Approach Utilized Concern: Failure of electrical components (primarily leads of large chips) due to fatigue Analysis Completed on Individual Frames and PFDPU Assy UCB (Pankow) for DEB, REG, SEP, IIB LASP/GSFC for MAG, DFB, REG Analysis reviewed and approved by Project Project Design Guidelines Established Individual Cards redesigned to increase stiffness Max card stiffness below 300 Hz PFDPU Structural Packaging stiffness increased Minimum 600 Hz (2 X 300 Hz) Per Steinberg approach

  23. Box Structural Enhancements Frame Side Walls Thickness Increased; New Shear Panels Introduced • PCBs bonded to Frames • Hysol EA9309 w/ Boron Nitride Filler • SEP, REG, IIB, DCB • Increases Box Stiffness • Allows better thermal path to Frames New 2 X Side Shear Panels, .080” Thick (6061 T6) LASP/GSFC Cards Frames redesigned by host organizations to stiffen frames Each Side Box Frame Walls Thickness increased to .150” (was: .100”) (6061 T6) 4-40 Screws and Washers

  24. PFDPU Vibration Testing Test Procedure MAVEN_PF_TP_042_PFDPU_Vibration_Test Scheduled for August 2012 First test of completed Unit Protoflight Hardware Hardware to be kept clean by bagging Standard Test Protocols Pass/Fail Criteria Box unpowered throughout testing Pre- and Post- electrical checkout to be performed at SSL

  25. MAVEN PFDPU TVAC Testing

  26. PFDPU TVAC Testing Test Procedure MAVEN_PF_TP_044_PFDPU_Thermal_Vac_Test Scheduled for August - September 2012 PFDPU TVAC to be performed in SSL Chamber (Snout 1) Hardware to be kept clean by bagging during transfer to Thermal VAC Chamber Overview has been presented by Thermal Engineer One non-op cycle from –30 to +60C 7 operational cycles from –30 to +50C (as measured at the baseplate) Bakeout at 60C following the Electrical Testing

  27. PFDPU TVAC Cycles Cycle Number: 1 2 3 4 5 6 7 3 7 6 2 1 9 5 n 8 4 Performance test executed at each hot and cold plateau CPT (performed at first and last hot/cold cycles) verifies both redundant sections of the PFDPU, along with PFDPU resident instrument functionality (such as Actuators and Heater subsystems) Flight Magnetometers in chamber with PFDPU for TVAC qualification

  28. PFDPU TVAC Functional Plan Overview

  29. PFDPU TVAC Hardware/GSE Configuration

  30. PFDPU – Wrapup/Questions Much progress since CDR of May 2011 Flight Hardware has been built and associated risks retired Manufacturing: CGA624 manufacturing successful Mechanical: Improvements to PFDPU allay vibration concerns Thermal: Heat conduction path enhancements & lower than expected current draws Hardware/Software Integration validated with the ETU PFDPU Operates as a parallel/alternate PFDPU Testbed ETU Instruments have been combined into this setup Available for “dry runs” of the CPTs, RTSs and software testing High-Fidelity Simulator (ETU DCB and REG) functioning successfully at Lockheed-Martin since March’12 delivery Integration of Flight PFDPU proceeding Next Steps: Environmental Testing EMC => Vibration => Magnetics => TVAC

  31. Backup Particle and Fields Data Processing Unit

  32. Controlling Documents Mission Requirements MAVEN_PF_QA_002, PFP Mission Assurance Implementation Plan MAVEN-PM-RQMT-0005D_MRD.xlsx MAVEN-PFIS-RQMT-0016D+_2-7-2011.xlsx MAVEN_PF_SYS_033B_VerificationMatrix.xlsx Systems Requirements Document MAVEN_PF_SYS_003 – Power Converter Requirements MAVEN-SYS-RQMT-0010 – Environment Requirements Interface Control Documents MAVEN_PF_SYS_004I_PFDPUtoInstrumentICD MAVEN-SC-ICD-0007 - Spacecraft to PF ICD MAV-IDP-MEC-003 MAVEN PFDPU MICD

  33. PFDPU Driving Requirements (1)

  34. PFDPU Driving Requirements (2)

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