Final presentation – part B

1. FPGA Setting Using Flash Final presentation – part B Bi – semester project DorObstbaum and Kami Elbaz Advisor: Moshe Porian November 2012

2. FPGA Setting Using Flash Project movie

3. Content Introduction • Introduction • Display • FLASH • Performance • Configuration • Testability • GUI • Conclusions Display FLASH Performance Configuration Testability GUI and p&r Conclusions

4. Motivation Introduction • Hardware operates by configuration written in the registers Display • Software writes up to date configuration in the FLASH memory FLASH Performance Configuration • FPGA setting using FLASH system does the connection Testability GUI and p&r Conclusions FPGA setting using FLASH system FLASH memory registers Software Independent! Software Host Hardware System

5. TOP Architecture Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

6. What have we achieved in part B of the project? Introduction Display • CFI interface with FLASH memory • Automatic configuration of clients using data base stored in FLASH • Wishbone Bus upgrade for enhancing system performance • Watchdog and Power features added • GUI with abundant capabilities FLASH Performance Configuration Testability GUI and p&r Conclusions

7. Display client 1024 • Technical Demands: • VESA protocol • Operates on a 65 MHz clock • Produces 3 kinds of pictures: lines, columns, damka squares • control frame ROI and shape width and color • Supports any kind of Resolution and timing by Generics • Inputs: Wishbone interface to configure registers • Outputs: RGB, hsync, vsync, blank Introduction Display FLASH Performance 768 Configuration Testability GUI and p&r Conclusions Our Configuration

8. Display client Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions Integrated from RunLen project 100 MHz 65 MHz

9. Display client Enable Lines Introduction Line ROI Display Line width Line color diff FLASH RGB start val Performance Enable Lines Configuration Line ROI Testability Line width RGB GUI and p&r Conclusions Line color diff Integrated from RunLen project RGB start val

10. Display client Introduction We Want Our Frames like These: Display FLASH Performance Configuration Testability And NOTlike these: GUI and p&r Conclusions How do we keep Synchronization when registers Are updated?

11. Synthetic Data Provider Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

12. Waveform Introduction Display Wishbone transactions configures registers FLASH Performance Configuration Testability Register Valid is ‘0’ while registers are updated GUI and p&r Conclusions VESA generator requests data for a new frame Valid Data is supplied after 1 cycle

13. FLASH Memory Introduction Display FLASH Performance Configuration Testability GUI Conclusions

14. FLASH Client Introduction BUS • Technical Demands: • Common FLASH Interface protocol (CFI) • Wishbone Interface • Performs Read, Write, Reset and Erase transactions • Initiative read on power-on • Contains a timeout algorithm • Generic: adaptable to different FLASH sizes and clock frequencies. Display CFI FLASH Wishbone Performance Configuration Testability GUI and p&r Conclusions

15. FLASH Client block diagram Initiative read for configuration System power on Introduction Display FLASH FLASH Read address 0x000000 Performance Configuration Testability GUI and p&r Conclusions

16. Write transaction Introduction Display FLASH FLASH Write command Performance Configuration Testability GUI and p&r BUS transaction ends. Client enters stall mode while writing data to FLASH. Conclusions

17. Performance – Wishbone upgrade Wishbone Bus – Old version Introduction Control unit Wishbone Master Wishbone Slave Registers Standard bus Display FLASH Address advancer Performance RAM Configuration Testability GUI and p&r FSM FSM FSM FSM Wishbone Bus – New version Conclusions • Simple interface • Enhanced performance • Less logic elements • Contains Watchdog Wishbone Master Wishbone Slave Registers Pipeline bus start done RAM

18. Performance enhancement Old version Introduction Display FLASH Performance Configuration • Throughput: 1/12 [bytes/cycle] Testability New version GUI and p&r Conclusions • Throughput: 1 [bytes/cycle]

19. Simple Interface – RX path example Old version MDWM mediates between mp-decoder, wishbone master and RAM Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions New version No need for MDWM

20. Configuration Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

21. Config Control Block • Reads data from FLASH into internal RAM • Configures clients using Wishbone bus transactions • Option for re-configuration • Option for unit disable Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

22. Testability – Test plan Introduction • All FLASH transactions • Correct configuration of clients • Generic system • System boundaries • Hardware tests Display FLASH Performance Configuration Testability GUI and p&r Conclusions

23. Test environment Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

24. GUI - Capabilities • Operational features: • Read, Write and erase transactions to FLASH • Data abstraction – very little knowledge needed for operation • Data base creation – for storing in FLASH • Direct transaction to clients • Easy work with text files • Generates only correct packets with legal values Introduction Display FLASH Performance Configuration Testability • Debug features: • TX and RX messages display • Option for changing or removing CRC/EOF/SOF • Generates text files available for simulation GUI and p&r Conclusions GUI user guide included

25. GUI appearance Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

26. Synthesis results Introduction Display FLASH Performance Configuration Testability GUI and p&r Conclusions

27. max frequency Introduction Display FLASH Performance Configuration Testability GUI and p&r • Required frequency: 100 MHz • Part A max frequency: 128.34 MHz • Part B max frequency: 134.25 MHz Conclusions Improvement of 4.6% from part A of the project

28. Possible Application Any hardware client can be connected to the system if it possesses a Wishbone Slave connection. Such a client could be a Pulse Width Modulator (PWM) . A PWM can define a unique frequency for many servo controllers. In order to prevent the case that on system power on there would be some default insufficient value on the frequency input of servo devices, the PWM will function as a client of the FPGA setting using FLASH system. Data would be loaded from the Flash memory for correct configuration.

29. What have we learned? Introduction • Planning and Specifying a Project • Writing reusable generic code • Protocols: UART, Wishbone, VESA, CFI • Read and understand Verilog code • Integration of many components • Verify logic correctness using waveforms, text files, BMP files and scripts • Testing our hardware using GUI and debug with signaltap • Documentation of the work done • SVN, Code Review and running a project diary are useful tools • Expect code to be used by others in the future Display FLASH Performance Configuration Testability GUI and p&r Conclusions

30. DEMO