Govindrao Wanjari College of Engineering & Technology,Nagpur Department of CSE Session: 2017-18

1. Govindrao Wanjari College of Engineering & Technology,NagpurDepartment of CSE Session: 2017-18 Branch/ Sem: CSE/4thsem“IBM 360/370 & Assembler” Subject :SP Subject Teacher: Prof.R.G.Gupta

2. CONTENTS • INTRODUCTION • CRITICAL ELEMENTS • ARCHITECTURE DETAILS • ADDRESSING MODES AND INSTRUCTION FORMATS • OPERATION ON THE 360/370

3. INTRODUCTION • The IBM System/360 (S/360) is a mainframe computer system family announced by IBM on April 7, 1964. It was the first family of computers designed to cover the complete range of applications, from small to large, both commercial and scientific. • The goal when creating the IBM 360 was to create a “family concept”, where for the first time a single ISA could be used with older and newer machines in the same family. • The IBM 360 was historically important due to 1. forward and backward compatibility (family concept and extensive instruction set) 2. clear separation between architecture and implementation 3. integration of scientific and business efficiency 4. extensive use of microprogramming

5. CRITICAL ELEMENTS • Forward and Backward Compatibility IBM wanted to create “general purpose” computers that were both forward and backward compatible. In doing so, they created small and large computers that could handle the same ISA. They had to find a middle ground between complicated and resource-intensive microinstructions that small computers couldn’t run effectively and simple instructions that didn’t utilize the large computers’ resources. The loss of efficiency in the computers due to compatibility design considerations was far overshadowed by the advantage of compatibility achieved between models. Hence, they could create software that fit a single product line and customers could choose their appropriate machine along this compatible line. The IBM 360 family of computers created the concept of the ISA , where every machine had the same set of instructions, number of user registers, and behavior, and thus were binary compatible

7. Clear Separation Between Architecture and Implementation The various capabilities and resources of one computer in the line versus another required different implementations, while using the same ISA. IBM used the same architecture throughout many different computers that then needed different implementations • Integration of Scientific and Business Efficiency Before the IBM 360, computers typically offered performance in either scientific or business constructs. The IBM 360 family of machines could run the same programs that were on separate computers earlier, but at different speeds. The tradeoff of performance for the ability to run business and scientific programs on the same machine was worthwhile. System/360 was designed to be able to handle both decimal and binary formatted information, with both variable-fixed length and floating-point arithmetic capabilities. Since scientific users tended to use Fortran and business users tended to use Cobol, IBM designed and developed the PL/1 programming language in a an attempt to provide a programming bridge between the two communities

8. Extensive Use of Microprogramming The architecture of the IBM 360 is built around microprogramming, or small programs of microinstructions. By using microprogramming, smaller and larger computers could accomplish goals of small micro programs with their own implementations and use whichever microinstructions best suited them (most efficiently, that is). This way the ISA is consistent, but separate efficient microprogramming techniques between models are the only difference. In order to accomplish this, there needs to be an extensive set of microinstructions that all of the different models of computers could use. Thus, the concept of a CISC (Complex Instruction Set Computing) architecture was created.

9. The 360/370 Instruction Set Architecture The IBM System/360 is a 32-bit machine with byte addressability and support for a variety of data types: byte, halfword (16 bits), word (32 bits), doubleword (double-precision real), packed decimal, and unpacked character strings. The System/360 had alignment restrictions, which were removed in the System/370 architecture. • The internal state of the 360 has the following components: 1. Sixteen 32-bit, general-purpose registers: register 0 is special when used in an addressing mode, where a zero is always substituted. 2.Four double-precision (64-bit) floating-point registers. 3.Program status word (PSW) holds the PC, some control flags, and the condition codes. 4.Later versions of the architecture extended this state with additional control registers.

10. Addressing Modes and Instruction Formats The 360/370 has five instruction formats. Each format is associated with a single addressing mode and has a set of operations defined for that format. While some operations are defined in multiple formats, most are not. • RR (register-register ) • RX (register-indexed) • RS (register-storage ) • SI (storage-immediate) • SS(storage-storage)

12. Operations on the 360/370 • The instructions on the 360 can be divided into classes. Four basic types of operations on data are supported: 1. Logical operations on hits, character strings, and fired words. These are mostly RR and RX formats with a few RS instructions. 2. Decimal or character operations on strings of characters or decimal digits. These are SS format instructions. 3. Fixed-point binary arithmetic. This is supported in both RR and RX formats. 4. Floating-point arithmetic. This is supported primarily with RR and RX instructions. Branches use the RX instruction format with the effective address specifying the branch target. Since branches are not PC-relative, a base register may need to be loaded to specify the branch target. This has a rather substantial impact: in general, it means that there must be registers that point to every region containing a branch target. The condition codes are set by all arithmetic and logical operations. Conditional branches test the condition codes under a mask to deter-mine whether or not to branch.

13. IBM System z10 • IBM System z10 is the latest line of IBM mainframes. The z10 Enterprise Class (EC) was announced on February 26, 2008. On October 21, 2008, IBM announced the z10 Business Class (BC), a scaled down version of the z10 EC. The System z10 represents the first model family powered by the z10 quad core processing engine and the first to implement z/Architecture 2 (ARCHLVL 3). • New Features • Cryptography • Decimal Floating Point • New Instructions • New Architecture Level Set (ALS) • z/VM LPAR Support • Capacity On Demand Enhancements

14. z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), refers to IBM's 64-bit computing architecture for the current generation of IBM mainframe computers. IBM introduced its first z/Architecture-based system, the zSeries Model 900, in late 2000. Later z/Architecture systems included the IBM z800, z990, z890, System z9 and the System z10. z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors all the way back to the 32-bit-data/24-bit-addressing System/360.

15. Enterprise Class

16. Business Class

18. Reference • http://en.wikipedia.org/wiki/IBM_System/360 • http://domino.watson.ibm.com/tchjr/journalindex.nsf/ResSubject?OpenView&RestrictToCategory=IBM%20System/360 • http://cis.poly.edu/cs2214rvs/ibm.htm • http://www.beagle-ears.com/lars/engineer/comphist/ibm360.htm • http://www-sst.informatik.tu-cottbus.de/~db/doc/People/Broy/Software-Pioneers/Brooks_new.pdf

19. Govindrao Wanjari College of Engineering & Technology,NagpurDepartment of CSE Session: 2017-18 Branch/ Sem: CSE/6thsem“MACRO PROCESSOR” Subject :SP Subject Teacher: Prof.R.G.Gupta

20. Introduction • A macro instruction (abbreviated to macro) is simply a notational convenience for the programmer. • A macro represents a commonly used group of statements in the source programming language • Expanding a macros • Replace each macro instruction with the corresponding group of source language statements

21. Introduction (Cont’d) • E.g. • On SIC/XE requires a sequence of seven instructions to save the contents of all registers • Write one statement like SAVERGS • A macro processor is not directly related to the architecture of the computer on which it is to run • Macro processors can also be used with high-level programming languages, OS command languages, etc.

22. Basic Macro Processor Functions Expanded program A program with Macro definitions and Macro invocations Macro Processor A program without Macro definitions Assembler Object program

23. Basic Macro Processor Functions • Macro Definition • Two new assembler directives • MACRO • MEND • A pattern or prototype for the macro instruction • Macro name and parameters • See figure 4.1

25. Basic Macro Processor Functions • Macro invocation • Often referred to as a macro call • Need the name of the macro instruction begin invoked and the arguments to be used in expanding the macro • Expanded program • Figure 4.2 • No macro instruction definitions • Each macro invocation statement has been expanded into the statements that form the body of the macro, with the arguments from the macro invocation substituted for the parameters in the prototype

27. Basic Macro Processor Functions • Macro invocations and subroutine calls are different • Note also that the macro instructions have been written so that the body of the macro contains no label • Why?

28. Macro Processor Algorithm and Data Structures • It is easy to design a two-pass macro processor • Pass 1: • All macro definitions are processed • Pass 2: • All macro invocation statements are expanded • However, a two-pass macro processor would not allow the body of one macro instruction to contain definitions of other macros • See Figure 4.3

30. Macro Processor Algorithm and Data Structures • Sub-Macro definitions are only processed when an invocation of their Super-Macros are expanded • See Figure 4.3: RDBUFF • A one-pass macro processor that can alternate between macro definition and macro expansions able to handle macros like those in Figure 4.3

31. Macro Processor Algorithm and Data Structures • Because of the one-pass structure, the definition of a macro must appear in the source program before any statements that invoke that macro • Three main data structures involved in an one-pass macro processor • DEFTAB, NAMTAB, ARGTAB

35. Machine-Independent Macro Processor Feature • Concatenation of Macro Parameters • Generation of Unique Labels • Conditional Macro Expansion • Keyword Macro Parameters

36. Concatenation of Macro Parameters • Most macro processors allow parameters to be concatenated with other character strings • The need of a special catenation operator • LDA X&ID1 • LDA X&ID • The catenation operator • LDA X&ID1 • See figure 4.6

38. Generation of Unique Labels • It is in general not possible for the body of a macro instruction to contain labels of the usual kind • Leading to the use of relative addressing at the source statement level • Only be acceptable for short jumps • Solution: • Allowing the creation of special types of labels within macro instructions • See Figure 4.7

40. Generation of Unique Labels • Solution: • Allowing the creation of special types of labels within macro instructions • See Figure 4.7 • Labels used within he macro body begin with the special character $ • Programmers are instructed no to use $ in their source programs

41. Conditional Macro Expansion • Most macro processors can modify the sequence of statements generated for a macro expansion, depending on the arguments supplied in the macro invocation • See Figure 4.8

44. Conditional Macro Expansion • Most macro processors can modify the sequence of statements generated for a macro expansion, depending on the arguments supplied in the macro invocation • See Figure 4.8 • Macro processor directive • IF, ELSE, ENDIF • SET • Macro-time variable (set symbol) • WHILE-ENDW • See Figure 4.9

46. Keyword Macro Parameters • Positional parameters • Parameters and arguments were associated with each other according to their positions in the macro prototype and the macro invocation statement • Consecutive commas is necessary for a null argument GENER ,,DIRECT,,,,,,3

47. Keyword Macro Parameters • Keyword parameters • Each argument value is written with a keyword that names the corresponding parameter • A macro may have a large number of parameters , and only a few of these are given values in a typical invocation GENER TYPE=DIRECT, CHANNEL=3

50. Macro Processor Design Options • Recursive Macro Expansion • In Figure 4.3, we presented an example of the definition of on macro instruction by another. • We have not dealt with the invocation of one macro by another (nested macro invocation) • See Figure 4.11