AXI Interfacing Using DMA & AXI4-Stream

1. ECE 699: Lecture 6 AXI Interfacing Using DMA & AXI4-Stream

2. Required Reading The ZYNQ Book • Chapter 19: AXI Interfacing • Chapter 2.3: Processing System – • Programmable Logic Interfaces • Chapter 9.3: Buses • Chapter 10.1: Interfacing and Signals

3. Required Reading ARM AMBA AXI Protocol v1.0: Specification • Chapter 1: Introduction • Chapter 2: Signal Descriptions • Chapter 3: Channel Handshake • Chapter 4: Addressing Options • Chapter 9: Data Buses

4. Recommended Reading P. Schaumont, A Practical Introduction to Hardware/Software Codesign, 2nd Ed. • Chapter 10: On-Chip Buses M.S. Sadri, ZYNQ Training (presentations and videos) • Lesson 1 : What is AXI? • Lesson 2 : What is an AXI Interconnect? • Lesson 3 : AXI Stream Interface

5. Components of Today’s Systems-on-Chip Source: M.S. Sadri, Zynq Training

6. Connectivity Requirements Source: M.S. Sadri, Zynq Training

7. SoC Buses Source: M.S. Sadri, Zynq Training

8. Solution Adopted in ZYNQ Advanced Microcontroller Bus Architecture (AMBA): an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. First version introduced by ARM in 1996. AMBA Advanced eXtensible Interface 4 (AXI4): the fourth generation of AMBA interface defined in the AMBA 4 specification, targeted at high performance, high clock frequency systems. Introduced by ARM in 2010. Source: M.S. Sadri, Zynq Training

9. Basic Concepts Source: M.S. Sadri, Zynq Training

10. Communication BetweenAXI Master and AXI Slave Source: M.S. Sadri, Zynq Training

11. Additional Information Exchanged BetweenAXI Master and AXI Slave Source: M.S. Sadri, Zynq Training

12. Five Channels of AXI Interface Source: M.S. Sadri, Zynq Training

13. Connecting Masters and Slaves Source: M.S. Sadri, Zynq Training

14. AXI Interconnect

15. Interconnect vs. Interface

16. AXI Interfaces and Interconnects Interface A point-to-point connection for passing data, addresses, and hand-shaking signals between master and slave clients within the system Interconnect A switch which manages and directs traffic between attached AXI interfaces Source: The Zynq Book

17. Addressing of Slaves Source: M.S. Sadri, Zynq Training

18. AXI Interconnect Address Decoding Source: M.S. Sadri, Zynq Training

19. Clock Domain and Width Conversion Source: M.S. Sadri, Zynq Training

20. Hierarchical AXI Interconnects Source: M.S. Sadri, Zynq Training

21. Simple Address Definition Rules No Overlaps Source: M.S. Sadri, Zynq Training

22. Simple Address Definition Rules Address Alignment

23. Point-to-Point Data Flows Source: M.S. Sadri, Zynq Training

24. AXI Memory-Mapped vs. AXI Stream Source: M.S. Sadri, Zynq Training

25. Selected AXI Stream Ports Source: M.S. Sadri, Zynq Training

26. AXI Port Naming Conventions Source: M.S. Sadri, Zynq Training

27. AXI Interfaces (High-Performance) (Shared Bus) (Peripheral) (Point-to-Point Bus) Source: M.S. Sadri, Zynq Training

28. Concept of a Burst Source: M.S. Sadri, Zynq Training

29. Competing System-on-Chip Bus Standards AMBA: Advanced Microcontroller Bus Architecture AXI: Advanced eXtensible Interface AHB: AMBA High-speed Bus APB: AMBA Peripheral Bus PLB: Processor Local Bus OPB: On-chip Peripheral Bus MM: Memory Mapped ST: Streaming Source: A Practical Introduction to Hardware/Software Codesign

30. AXI4 Write Source: The Zynq Book

31. AXI4 Read Source: The Zynq Book

32. AXI4 Interface Write Address Channel Write Data Channel Write Response Channel Read Address Channel Read Data Channel Source: The Zynq Book

33. Prefixes of Ports from Particular Channels Source: The Zynq Book

34. Timing Diagram Conventions Source: ARM AMBA AXI Protocol v1.0: Specification

35. VALID before READY Handshake SRC SRC DST Source: ARM AMBA AXI Protocol v1.0: Specification

36. READY before VALID Handshake SRC SRC DST Source: ARM AMBA AXI Protocol v1.0: Specification

37. VALID with READY Handshake SRC SRC DST Source: ARM AMBA AXI Protocol v1.0: Specification

38. Channel Architecture of Reads Source: ARM AMBA AXI Protocol v1.0: Specification

39. Read Burst M M S S S S M Source: ARM AMBA AXI Protocol v1.0: Specification

40. Overlapping Read Bursts M M S S S S M Source: ARM AMBA AXI Protocol v1.0: Specification

41. Read Transaction Handshake Dependencies S M S M

42. Channel Architecture of Writes

43. Write Burst M M S M M M S S S M Source: ARM AMBA AXI Protocol v1.0: Specification

44. Write Transaction Handshake Dependencies M M S S M S Source: ARM AMBA AXI Protocol v1.0: Specification

45. Source: ARM AMBA AXI Protocol v1.0: Specification

46. Role of Write Strobe WSTRB WSTRB[n] corresponds to WDATA[8*n+7 downto 8*n] Source: ARM AMBA AXI Protocol v1.0: Specification

47. Narrow Transfer Example with 8-bit Transfers Source: ARM AMBA AXI Protocol v1.0: Specification

48. Narrow Transfer Example with 32-bit Transfers Source: ARM AMBA AXI Protocol v1.0: Specification

49. Aligned and Unaligned Word Transfers on a 32-bit Bus Source: ARM AMBA AXI Protocol v1.0: Specification

50. Aligned and Unaligned Word Transfers on a 64-bit Bus Source: ARM AMBA AXI Protocol v1.0: Specification