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Types of Instruction

Types of Instruction. ADD R ADD M (ADD REGISTER TO ACCUMULATOR). ADD B. AFTER EXECUTION. BEFORE EXECUTION. 98. ADD M. 65. BA. 55. 20. 50. ADC R ADC M (ADD REGISTER TO ACCUMULATOR WITH CARRY). ADD B. 1. BEFORE EXECUTION. AFTER EXECUTION. 98. 99. ADC M. 65. BEFORE EXECUTION.

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Types of Instruction

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  1. Types of Instruction

  2. ADD RADD M (ADD REGISTER TO ACCUMULATOR) ADD B AFTER EXECUTION BEFORE EXECUTION 98 LAKSHMI B.E.

  3. ADD M 65 BA 55 20 50 LAKSHMI B.E.

  4. ADC RADC M (ADD REGISTER TO ACCUMULATOR WITH CARRY) ADD B 1 BEFORE EXECUTION AFTER EXECUTION 98 99 LAKSHMI B.E.

  5. ADC M 65 BEFORE EXECUTION 1 AFTER EXECUTION 55 20 50 BA BB LAKSHMI B.E.

  6. ADI 8BITDATA [AA + 8BITDATA]ACI 8 BIT DATA[AA + C +8 BIT DATA LAKSHMI B.E.

  7. DAD REG PAIR DAD H BEFORE EXECUTION 20 50 20 50 + 40 A0 AFTER EXECUTION A0 40 50 20 LAKSHMI B.E.

  8. SUBTRACTION • SUB R ; SUB R; REGISTER A A-C ;SUB REG • SUB M ; SUB H ;AA-H ;SUB MEMORY • SUI DATA; AA-DATA ;SUB IMMEDIATE DATA • SBB R ;SBB C ;AA-C-CARRY;SUB REG WITH BORROW • SBB M ;SBB H ;AA-(H)(L)-CY ;SUB MEM WITH BORROW • SBI DATA ; AA-DATA-CY;SUB IMMEDIATE • WITH BORROW LAKSHMI B.E.

  9. INR R • INR B 36 LAKSHMI B.E.

  10. INR M • INR H LAKSHMI B.E.

  11. INX REG PAIR • INX D LAKSHMI B.E.

  12. SIMILARLY…… • DCR R • DCR M • DCX REG PAIR LAKSHMI B.E.

  13. LOGIC OPERATIONS • ANI DATA ;[AA DATA] • ANA M ;[AA (H)(L)] • ANA R; [ A A R] LAKSHMI B.E.

  14. LOGIC OPERATIONS • ORI DATA ;[AA DATA] • ORA M ;[AA (H)(L)] • ORA R; [ A A R] LAKSHMI B.E.

  15. LOGIC OPERATIONS • XRI DATA ;[AA DATA] • XRA M ;[AA (H)(L)] • XRA R; [ A A R] LAKSHMI B.E.

  16. CMP B; COMPARE REGISTER A (A-B) • CMP M; COMPARE MEMORY A(A-(H)(L)) • CPI DATA; COMPARE IMMEDIATE A(A-DATA) • CMA (COMPLEMENT ACC) • CMC (COMPLEMENT CARRY) • STC (SET CARRY) LAKSHMI B.E.

  17. RAL(ROTATE ACC LEFT THROUGH CARRY) A88H(1000 1000B) • CY1 at start • AFTER EXECUTION A D0D1,D7CARRY ,CARRYD0) 0 0 1 0 0 0 1 0 1 RAR (ROTATE ACC RIGHT THROUGH CARRY)similarly D7D6,D0CARRY ,CARRYD7) LAKSHMI B.E.

  18. RLC(ROT ACC LEFT TO CARRY)A88H(1000 1000B) • CY0 AT START • AFTER EXECUTION A11H (D7D0,D0D1,D7CARRY ) 0 0 1 0 0 0 1 0 0 RRC(ROTATE ACCUMULATOR RIGHT)SIMILARLY (D7D6,D0D7,D0CARRY LAKSHMI B.E.

  19. DATA SERIALISATION P1.0 1 0 0 0 1 1 0 0 0

  20. J CONDITION LAKSHMI B.E.

  21. C CONDITION LAKSHMI B.E.

  22. CONTROL AND STATUS SIGNAL LAKSHMI B.E.

  23. MACHINE CYCLE • A particular microprocessor requires a definite time to performing a specific task. This time is called machine cycle. • Instruction cycle(PROCESSOR CYCLE)is defined as the time required to fetch and execute an instruction. • The function of the microprocessor is divided into fetch and execute cycle of any instruction of a program. • The program is nothing but number of instructions stored in the memory in sequence. LAKSHMI B.E.

  24. MACHINE CYCLE • Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC) LAKSHMI B.E.

  25. MACHINE CYCLE • It is well known that an instruction cycle consists of many machine cycles. • Each machine cycle consists of many clock periods or cycles, called T-states. LAKSHMI B.E.

  26. OPCODE FETCH(M1) • The 1st machine cycle (M1) of every instruction cycle is the opcode fetch cycle. • during (M1 cycle) • puts the program counter contents on the address bus • reads the opcode of the instruction through read process LAKSHMI B.E.

  27. OPCODE FETCH LAKSHMI B.E.

  28. LAKSHMI B.E.

  29. R CONDITION LAKSHMI B.E.

  30. In T2, the RD control signal becomes low to enable the memory for read operation. • A low IO/M means microprocessor wants to communicate with memory. • The μP sends a high on status signal S1 and S0 indicating fetch operation. • The μP sends 16-bit address. AD bus has address in 1st clock of the 1st machine cycle,T1. • AD7 to AD0 address is latched in the external latch when ALE = 1. • AD bus now can carry data. LAKSHMI B.E.

  31. • The memory places opcode on the AD bus • • The data is placed in the data register (DR) and then it is transferred to IR. • • During T3 the RD signal becomes high and memory is disabled. • • During T4 the opcode is sent for decoding and decoded in T4. • • The execution is also completed in T4 if the instruction is single byte. LAKSHMI B.E.

  32. Memory read machine cycle LAKSHMI B.E.

  33. Memory write machine cycle LAKSHMI B.E.

  34. IO READ MACHINE CYCLE LAKSHMI B.E.

  35. IO WRITE MACHINE CYCLE LAKSHMI B.E.

  36. MOV B,C LAKSHMI B.E.

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