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Lab 9 PowerPoint Presentation

Lab 9

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Lab 9

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  1. Lab 9 • RT methodology introduction • Register operations • Data Path • Control Path • ASM • Example TA: Jorge Crichigno

  2. RT Methodology The circuits we have designed so far did not have any particular structure and were implemented as structural data flow. The structural data flow implementation is not general and can be applied only for simple, trivial systems. The register transfer (RT) methodology is a powerful technique, intended for developing complex digital circuits

  3. RT Methodology • The key characteristics of the RT methodology are: • Use registers to store intermediate data. • Use a data path to realize all the required operations. The data path consists of processing logic and a collection of registers that perform data processing. • Use a control path to specify the order of the register operations. The control path is made up of logic that determines the sequence of data-processing operations performed by the data-path.

  4. RT Methodology • Basic RT operations • Register transfer operations are the elementary data-processing actions. • They are also referred as micro-operations. Register transfers move information between registers, between registers and memory, and through processing logic. • Dedicated transfer hardware using multiplexers and shared transfer hardware called buses implement these movement of data.

  5. Notation of RT operations rdest ← f (rsrc1, rsrc2, …, rsrcn) No restriction of the function f, as long as it can be designed as a circuit Example: r1 ← r1 + r2 r1_next Tcq: clock-to-q delay Note that the system clock is implicitly embedded in an RT operation (major difference between a register and a variable of regular programming languages).

  6. Multiple RT operations and Data Path Consider the following RT operations, which use r1 as the destination register: r1 ← 1, r1 ← r1 + r2, r1 ← r2 + 1, , r1 ← r1 An associated data path for these operations may be implemented as follows Control Path Control signals

  7. Control Path A control path is used to enforce the order of RT operations by generating the corresponding control signals. An FSM is a natural match for this task 1- Since the state transition is performed on a clock-by-clock basis, this naturally matches RT operations, which are also updated on a clock-by-clock basis. 2- Because of (1), RT operations can be specified in a state of the FSM, which can enforce a specific sequence of actions. 3- Upon an examination of input conditions, an FSM can branch to different paths and thus can alter the sequence of actions. This can be used to implement various branch constructs, such as the if and loop statements of an algorithm.

  8. ASM Chart An algorithm state machine (ASM), is an alternative method for representing an FSM. Although an ASM chart contains the same amount of information as a state diagram, it is more descriptive. It is usually used to specify complex sequence of events and actions needed to implement a control path. An ASM is composed of a network of ASM blocks.

  9. ASM Block

  10. ASM Block To reduce clutter, sometimes only the signals that are activated of asserted are shown in the ASM. Example 1:

  11. ASM Block Example 2:

  12. ASM Block Example 3:

  13. Example: a counter Specification: When start = 1 and reset = 0, the system starts counting at each rising edge. If inc = 0, counter is incremented by one; otherwise, it is incremented by two. A synchronous reset is implemented to reset the counter to zero. counter represents the current value of the counter. When counter reaches a value of six or greater, the output end is set to one for a clock period and the counter stops. Finally, the counter is set to zero and the system waits for start = 1 again. Register to be used Counter

  14. A data-path for the counter

  15. A control path for the counter

  16. Lab Task Given the data and control path shown before, your task consists of: 1- designing both data and control path in VHDL; 2- incorporating the designed control path and the data path into the counter system (top.vhd); 3- simulating the system and show to the TA the simulation results. The figure below shows how the final system would look like. Then, implement it on the FPGA board.