1 / 10

DAQ Overview + selected Topics

DAQ Overview + selected Topics. Beat Jost Cern EP. Overall Architecture. LHC-B Detector. Data rates. VDET TRACK ECAL HCAL MUON RICH. 40 MHz. Level 0 Trigger. 40 TB/s. Front-End Electronics. 1 MHz. Timing & Fast Control. L0. Fixed latency 4.0 m s. 1 TB/s.

mfishburn
Télécharger la présentation

DAQ Overview + selected Topics

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DAQ Overview+ selected Topics Beat Jost Cern EP

  2. Overall Architecture LHC-B Detector Data rates VDET TRACK ECAL HCAL MUON RICH 40 MHz Level 0 Trigger 40 TB/s Front-End Electronics 1 MHz Timing & Fast Control L0 Fixed latency 4.0 ms 1 TB/s 40 kHz L1 Level 1 Trigger Front-End Multiplexers (FEM) LAN 1 MHz Front End Links Variable latency <1 ms 4 GB/s RU RU RU Read-out units (RU) Throttle Read-out Network (RN) 2-4 GB/s Trigger Level 2 & 3 Event Filter SFC SFC Sub-Farm Controllers (SFC) Control & Monitoring Variable latency L2 ~10 ms L3 ~200 ms Storage 20 MB/s CPU CPU CPU CPU FE/Controls/DAQ Workshop 2000

  3. Event Builder Architecture FE/Controls/DAQ Workshop 2000

  4. Event Building Protocol • Pure “push” protocol • Each source (RU) of the event-builder sends data autonomously to a destination as soon as they are available • The destination is assigned through a static algorithm based on the event number. The identical algorithm runs in all sources (belonging to the same partition) -> The RUs belong to only one partition • The destinations (SFCs) receive the the fragments of the RUs and assemble them to form complete events. The SFCs will be configured to treat only fragments from the sources of the same partition -> The SFCs belong to only one partition • No communication (other than event fragments) between RUs and SFCs FE/Controls/DAQ Workshop 2000

  5. Event Fragment Assembly • The current idea is that the SFCs will be equipped with intelligent NICs (Network Interface Cards) • The NICs will handle all the fragment assembly to form complete events. • The host computer will only receive fully assembled events (or events flagged as erroneous) -> load on host reduced by ~100 (number of SFCs). SFC SNIC CPU Readout Network PCI Bus Controls Network Bridge NIC MEM Local Bus NIC Subfarm Network FE/Controls/DAQ Workshop 2000

  6. SFC Functionality • Assemble complete events • Monitor the state of the CPUs connected to it, implement dynamic load balancing among them and send raw data to ‘free’ CPUs • Receive the accepted and reconstructed events from the CPUs and send them to the storage controller • Monitor the buffer occupancy in the sub-farm and issue L1-Throttle in case buffers start getting full • Provide monitoring information to ECS FE/Controls/DAQ Workshop 2000

  7. Data Flow FE/Controls/DAQ Workshop 2000

  8. Readout Network Technologies Limit speed of end-node connections to ~1 Gb/s Current Candidate Technologies • ATM • ‘no’ smart NICs • enough performance • too expensive • Myrinet • smart NICs exist • works in principle • cheap switches, ~expensive interfaces • No buffering in switches • have to cascade switches -> have to build FIFOs to put between levels of switches (scalability) • Gb Ethernet • under study • has smart NICs • prob. works • cheap • Prob. have to cascade switches, should improve with 10GbE FE/Controls/DAQ Workshop 2000

  9. Other Networks • Data Network • Cheapest possible compatible with performance requirements • Input rate into CPU: ~5 MB/s • Output rate from CPU: ~25 kB/s • Fast Ethernet should be sufficient • Controls Network • Cheapest possible (prob. Fast Ethernet) FE/Controls/DAQ Workshop 2000

  10. Open Issues • Non Zero-suppressed readout • Memory on smart NICs is limited (currently 1 MB, including code) • Possible solution could be to do fragment assembly in the SFC itself? (Not too nice…) FE/Controls/DAQ Workshop 2000

More Related