1 / 6

X-Stack Energy Optimization: Fact or Fiction

X-Stack Energy Optimization: Fact or Fiction. Todd Austin University of Michigan. Austin’s Theory of Inevitable H/W Progression. Software Construction. Static circuit optimization. Typical-case optimization. Basic logic synthesis. X-Stack. Hand-drawn circuits. Hardware Construction.

mira
Télécharger la présentation

X-Stack Energy Optimization: Fact or Fiction

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. X-Stack Energy Optimization:Fact or Fiction Todd Austin University of Michigan

  2. Austin’s Theory of Inevitable H/W Progression Software Construction • Static circuitoptimization • Typical-caseoptimization • Basic logicsynthesis X-Stack • Hand-drawncircuits Hardware Construction

  3. Razor Typical-Case Optimization clk D1 Q1 0 Main Flip-Flop Razor FF Stabilizer FF PC Razor FF Razor FF Razor FF 1 Error_L Shadow Latch comparator IF ID EX MEM (read-only) WB (reg/mem) Error RAZOR FF clk_del bubble bubble bubble error error bubble error error recover recover recover recover Flush Control flushID flushID flushID flushID • Circuit-level Razor latch detects timing errors • Architecture-level pipeline recovery sequence fixes pipeline state after timing error • Operating system-level voltage control sets energy level to minimize error rates • 50% energy savings for < 1% performance loss X-Stack

  4. CryptoManiac Typical-Case Optimization Logical Unit {tiny} XOR AND Pipelined 32-Bit MUL {long} 1K Byte SBOX Cache 32-Bit Adder 32-Bit Rotator {short} Logical Unit {tiny} XOR AND • Circuit-level functional unit design tucks pre- and post-Boolean ops into clock cycle • Architecture-levelISA extension exposes pre/post-ops • Application-level programming re-expresses algorithms to leverage optimization • 20% performance benefit (could recast as energy benefit) CM Proc X-Stack CM Proc In Q Out Q Req Scheduler requests results . . . CM Proc Keystore

  5. X-Stack Optimization Thoughts • Opportunities • Big design wins to be found for x-stack optimizations • Challenges • Approach destroys abstractions, places burdens on layers up the stack (e.g., architects and programmers) • Typically need to work outside of your comfort zone • Reviewers are often skeptical of x-stack modeling fidelity • Advice • Play well with others (seek effective collaborations) • Be open to learning new technologies/applications/fields • Be prepared to pursue physical demonstrations

  6. Austin’s Theory of Inevitable H/W Progression Software Construction • Static circuitoptimization • Typical-caseoptimization • Basic logicsynthesis X-Stack X-Stack • Hand-drawncircuits • ComposableH/W acceleration Hardware Construction

More Related