Hierarchical Design Methodology: Top-Down vs Bottom-Up Approach

1. Designing with Verilog EECS150 Spring 2008 – Lab Lecture #2 Chen Sun EECS150 Lab Lecture #2

2. Today • Hierarchical Design Methodology • Top-Down and Bottom-Up • Partitioning & Interfaces • Behavioral vs. Structural Verilog • Administrative Info • Blocking and Non-Blocking • Verilog and Hardware • Lab #2 • Primitives EECS150 Lab Lecture #2

3. Hierarchical Design Methodology • Divide and conquer approach • More efficient in terms of design productivity. • Hierarchy helps in management of large designs. • Hierarchy allows for design collaboration. • Design is broken to different modules. • Each designer is responsible of a set of modules EECS150 Lab Lecture #2

4. Top-Down vs. Bottom-Up (1) • Top-Down Design • Think of the top-level picture of the project • Identify main components/modules • Think of inter-module communication • Do not get bugged down with details EECS150 Lab Lecture #2

5. Top-Down vs. Bottom-Up (2) • Top-Down Design • Ends here: EECS150 Lab Lecture #2

6. Top-Down vs. Bottom-Up (3) • Bottom-Up Testing • Faster, Easier and Cheaper • Test each little component thoroughly • Allows you to easily replicate working components EECS150 Lab Lecture #2

7. Partitioning & Interfaces (1) • Partitioning • Break design into independent modules • Decide what modules make sense • This is crucial for successful implementation and management of your design. • Think of functional components when deciding on module boundaries. • Each module should be: • A reasonable size • Independently testable • Successful partitioning allows easier collaboration on a large project EECS150 Lab Lecture #2

8. Partitioning & Interfaces (2) • Interfaces • How different partitions talk to one another • A concise definition of signals and timing • Timing is vital, do NOT omit it • Must be clean • Don’t send useless signals across • Bad partitioning might hinder this • An interface is a contract • Lets other people use/reuse your module EECS150 Lab Lecture #2

9. Behavioral vs Structural (1) • Behavioral description describes functionality of design. It is independent of implementation. • There is a one-to-many mapping between a behavioral module and a structural module. • Structural description defines and decides on an implementation of a module. • Here we map the design to actual cells/gates. EECS150 Lab Lecture #2

10. Behavioral vs. Structural (2) • Rule of thumb: • Behavioral doesn’t have sub-components • Structural has sub-components: • Instantiated Modules • Instantiated Gates • Instantiated Primitives • Most modules are mixed • Obviously this is the most flexible EECS150 Lab Lecture #2

11. Behavioral vs. Structural (2) EECS150 Lab Lecture #2

12. Behavioral vs. Structural (3) EECS150 Lab Lecture #2

13. Administrative Info • Lab Grading • Get it in by the opening of the next lab • Partial credit will be given for incomplete labs • Card Key Access for All is coming soon! • Start looking for partners! EECS150 Lab Lecture #2

14. B C A D Q D Q Clock Blocking vs. Non-Blocking (1) Verilog Fragment Result always @ (a) begin b = a; c = b; end C = B = A A-----B-------C B = Old A C = Old B always @ (posedge Clock) begin b <= a; c <= b; end EECS150 Lab Lecture #2

15. Blocking vs. Non-Blocking (2) • Use Non-Blocking for FlipFlop Inference • posedge/negedge require Non-Blocking • Else simulation and synthesis wont match EECS150 Lab Lecture #2

16. Blocking vs. Non-Blocking (3) • If you use blocking for FlipFlops: YOU WILL NOT GET WHAT YOU WANT! always @ (posedge Clock) begin b = a; // b will go away c = b; // c will be a FlipFlop end // b isn’t needed at all EECS150 Lab Lecture #2

17. Blocking vs. Non-Blocking (4) Race Conditions file xyz.v: module XYZ(A, B, Clock); input B, Clock; output A; reg A; always @ (posedge Clock) A = B; endmodule file abc.v: module ABC(B, C, Clock); input C, Clock; output B; reg B; always @ (posedge Clock) B = C; endmodule THIS IS WRONG EECS150 Lab Lecture #2

18. Blocking vs. Non-Blocking (5) Race Conditions file xyz.v: module XYZ(A, B, Clock); input B, Clock; output A; reg A; always @ (posedge Clock) A <= B; endmodule file abc.v: module ABC(B, C, Clock); input C, Clock; output B; reg B; always @ (posedge Clock) B <= C; endmodule THIS IS CORRECT EECS150 Lab Lecture #2

19. Verilog and Hardware (1) assign Sum = A + B; reg [1:0] Sum; always @ (A or B) begin Sum = A + B; end EECS150 Lab Lecture #2

20. Verilog and Hardware (2) assign Out = Select ? A : B; reg [1:0] Out; always @ (Select or A or B) begin if (Select) Out = A; else Out = B; end EECS150 Lab Lecture #2

21. Verilog and Hardware (3) assign Out = Sub ? (A-B) : (A+B); reg [1:0] Out; always @ (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; end EECS150 Lab Lecture #2

22. Verilog and Hardware (4) reg [1:0] Out; always @ (posedge Clock) begin if (Reset) Out <= 2’b00; else Out <= In; end EECS150 Lab Lecture #2

23. Lab #2 (1) • Lab2Top • Accumulator • Stores sum of all inputs • Written in behavioral verilog • Same function as Lab1Circuit • Peak Detector • Stores largest of all inputs • Written in structural verilog EECS150 Lab Lecture #2

24. Lab #2 (2) EECS150 Lab Lecture #2

25. Lab #2 (3) Accumulator.v EECS150 Lab Lecture #2

26. Lab #2 (4) PeakDetector.v EECS150 Lab Lecture #2

27. Primitives (1) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2

28. Primitives (2) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2

29. Primitives (3) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2