VLSI Signal Processing
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Presentation Transcript
VLSI Signal Processing Y. V. Joshi SGGS Institute of Engineering and Technology, Nanded IUCEE Workshop presentation-YVJoshi
Introduction • Efficient implementation of signal processing algorithms required for real time signal processing • Many ways • Working at architectural level • Implementation level • Using Digital Signal Processors • Using FPGAs • Using Full custom design IUCEE Workshop presentation-YVJoshi
Typical DSP algorithms • Simple • Convolution/Correlation • Transformations- FFT/DCT/Wavelet • Digital filtering • Filter banks • Complex • Neuro Computing • Computer Vision • Artificial organ development • etc IUCEE Workshop presentation-YVJoshi
Applications • MP3 players • Mobiles • Embedded systems (automobiles, aircraft, satellite etc) • Robots • Projection systems • Biomedical/Life support systems • Communication systems- Software defined radios, etc IUCEE Workshop presentation-YVJoshi
Architectural level • Techniques of reducing the critical path • Pipelining and Parallel Processing • Retiming • Unfolding • Folding • Dependent on optimization in data flow graphs IUCEE Workshop presentation-YVJoshi
Implementation level-DS Processors • Selection of DSP based on application demand • Analog Devices DSP • TI DSP • Motorala DSP • Selection of Tools/Hardware platforms • Development of algorithms on DSP IUCEE Workshop presentation-YVJoshi
Implementation level-FPGA • Selection of FPGA based on application demand • Xilinx • Alterra • Selection of Tools/Hardware platforms • Development of algorithms for FPGA IUCEE Workshop presentation-YVJoshi
Implementation level-Full Custom VLSI based • Selection of EDA tool based on application demand • Cadence/Tanner/Laker • Selection of Design methodology • Development of layouts (LVS/DRC clean) • Chip mfg. IUCEE Workshop presentation-YVJoshi
Resources • Basic units • Adder • Multiplier and • A delay • Structures used in Signal processing • Simple Direct form/Transpose form • Cascade/Parallel • Digital two pair/Lattice • Single multiplier per order structure • Derived structures (low sensitivity to coefficient quantisation) IUCEE Workshop presentation-YVJoshi
Example • A second order notch filter • Using allpass structure IUCEE Workshop presentation-YVJoshi
Example (Contd…) • With values of • With being the notch frequency and being the rejection bandwidth • implementation with only two multipliers with minimum critical path IUCEE Workshop presentation-YVJoshi
Thanks Contact : Y. V. Joshi Yashwant.joshi@gmail.com IUCEE Workshop presentation-YVJoshi
