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Memory Cache Tracing Exercise Setup Information

Exercise #1 provides setup information for a memory cache tracing exercise involving memory address offsets, cache blocks, indexing tags, and memory content. Followed by Exercise #2 which traces memory access and cache loads using the setup provided.

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Memory Cache Tracing Exercise Setup Information

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  1. Direct Map Cache Tracing Exercise

  2. Exercise #1: Setup Information Memory 4GB Offset Offset Block Number Index Tag Memory Address Offset, N = Block Number = 31 N N-1 0 1 Block = 8 bytes N+M-1 31 N N-1 0 Cache 32Bytes Number of Cache Blocks = Cache Index, M = Cache Tag = 1 Block = 8 bytes Cache I

  3. Exercise #2: Tracing Memory Access Memory Content Cache I • Using the given setup, trace the following memory loads: • Load from addresses: 4, 0, 8, 12, 36, 0, 4 • Note that “A”, “B”…. “J” represents word-size data

  4. Exercise #2: Load #1 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 00 100 Address 4 = Cache I 

  5. Exercise #2: Load #2 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 00 000 Address 0 = Cache I 

  6. Exercise #2: Load #3 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 01 000 Address 8 = Cache I 

  7. Exercise #2: Load #4 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 01 100 Address 12 = Cache I 

  8. Exercise #2: Load #5 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000001 00 100 Address 36 = Cache I 

  9. Exercise #2: Load #6 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 00 000 Address 0 = Cache I 

  10. Exercise #2: Load #7 Tag Index Offset Addresses: 4, 0, 8, 12, 36, 0, 4 00000000000000000000000000 00 100 Address 4 = Cache I 

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