Package with 4-valued logic Signal Attributes Assertion Data Flow description

Package with 4-valued logic Signal Attributes Assertion Data Flow description

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Package with 4-valued logic Signal Attributes Assertion Data Flow description

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1. Package with 4-valued logic Signal Attributes Assertion Data Flow description

2. Few more Examples of Simulation • Build a library of logic gates • AND, OR, NAND, NOR, INV, etc. • Include sequential elements • DFF, Register, etc. • Include tri-state devices • Use 4-valued logic • ‘X’, ‘0’, ‘1’, ‘Z’ • Encapsulate global declarations in a package Our goal is to Explain 4-valued logic

3. Global Package • Build a library of logic gates • AND, OR, NAND, NOR, INV, etc. • Include sequential elements • DFF, Register, etc. • Include tri-state devices • Use 4-valued logic • ‘X’, ‘0’, ‘1’, ‘Z’ • Encapsulate global declarations in a package PACKAGE resources IS TYPE level IS ('X', '0', '1', 'Z'); -- enumerated type TYPE level_vector IS ARRAY (NATURAL RANGE <>) OF level; -- type for vectors (buses) SUBTYPE delay IS TIME; -- subtype for gate delays -- Function and procedure declarations go here END resources; Next we build gates

4. Two Input AND Gate Example ARCHITECTURE behav OF and2 IS BEGIN one : PROCESS (a,b) BEGIN IF (a = '1' AND b = '1') THEN c <= '1' AFTER trise; ELSIF (a = '0' OR b = '0') THEN c <= '0' AFTER tfall; ELSE c<= 'X' AFTER (trise+tfall)/2; END IF; END PROCESS one; END behav; USE work.resources.all; ENTITY and2 IS GENERIC(trise : delay := 10 ns; tfall : delay := 8 ns); PORT(a, b : IN level; c : OUT level); END and2; a b 1 and X = X c Observe that we use here three-valued algebra {0,1,X}

5. And Gate Simulation Results

6. Tri-State Buffer Example USE work.resources.all; ENTITY tri_state IS GENERIC(trise : delay := 6 ns; tfall : delay := 5 ns; thiz : delay := 8 ns); PORT(a : IN level; e : IN level; b : OUT level); END tri_state; ARCHITECTURE behav OF tri_state IS BEGIN one : PROCESS (a,e) BEGIN IF (e = '1' AND a = '1') THEN -- enabled and valid data b <= '1' AFTER trise; ELSIF (e = '1' AND a = '0') THEN b <= '0' AFTER tfall; ELSIF (e = '0') THEN -- disabled b <= 'Z' AFTER thiz; ELSE -- invalid data or enable b <= 'X' AFTER (trise+tfall)/2; END IF; END PROCESS one; END behav; b e Observe that we use here four-valued algebra {0,1,X,Z} a

7. Tri-State Buffer Simulation Results ARCHITECTURE behav OF tri_state IS BEGIN one : PROCESS (a,e) BEGIN IF (e = '1' AND a = '1') THEN -- enabled and valid data b <= '1' AFTER trise; ELSIF (e = '1' AND a = '0') THEN b <= '0' AFTER tfall; ELSIF (e = '0') THEN -- disabled b <= 'Z' AFTER thiz; ELSE -- invalid data or enable b <= 'X' AFTER (trise+tfall)/2; END IF; END PROCESS one; END behav; USE work.resources.all; ENTITY tri_state IS GENERIC(trise : delay := 6 ns; tfall : delay := 5 ns; thiz : delay := 8 ns); PORT(a : IN level; e : IN level; b : OUT level); END tri_state;

8. D Flip Flop Example USE work.resources.all; ENTITY dff IS GENERIC(tprop : delay := 8 ns; tsu : delay := 2 ns); PORT(d : IN level; clk : IN level; enable : IN level; q : OUT level; qn : OUT level); END dff; ARCHITECTURE behav OF dff IS BEGIN one : PROCESS (clk) BEGIN -- check for rising clock edge IF ((clk = '1' AND clk'LAST_VALUE = '0') AND enable = '1') THEN -- ff enabled -- first, check setup time requirement IF (d'STABLE(tsu)) THEN -- check valid input data IF (d = '0') THEN q <= '0' AFTER tprop; qn <= '1' AFTER tprop; ELSIF (d = '1') THEN q <= '1' AFTER tprop; qn <= '0' AFTER tprop; ELSE -- else invalid data q <= 'X'; qn <= 'X'; END IF; ELSE -- else violated setup time requirement q <= 'X'; qn <= 'X'; END IF; END IF; END PROCESS one; END behav;

9. D Flip Flop Simulation Results ARCHITECTURE behav OF dff IS BEGIN one : PROCESS (clk) BEGIN -- check for rising clock edge IF ((clk = '1' AND clk'LAST_VALUE = '0') AND enable = '1') THEN -- ff enabled -- first, check setup time requirement IF (d'STABLE(tsu)) THEN -- check valid input data IF (d = '0') THEN q <= '0' AFTER tprop; qn <= '1' AFTER tprop; ELSIF (d = '1') THEN q <= '1' AFTER tprop; qn <= '0' AFTER tprop; ELSE -- else invalid data q <= 'X'; qn <= 'X'; END IF; ELSE -- else violated setup time requirement q <= 'X'; qn <= 'X'; END IF; END IF; END PROCESS one; END behav; USE work.resources.all; ENTITY dff IS GENERIC(tprop : delay := 8 ns; tsu : delay := 2 ns); PORT(d : IN level; clk : IN level; enable : IN level; q : OUT level; qn : OUT level); END dff;

10. Assertion Statements assert condition report message severity level; • Ex. assert not (S = '1' and R = '1') report “S and R are equal to '1'” severity Error; • An assertion statement specifies a boolean condition to check, an error message and a severity indication.

11. Assertion Statements When the condition is false, the error message is sent to the system output with an indication of the severity and the name of the design unit in which the assertion occurred. • (Default message: “Assertion violation”). • The severity is of the type Severity_Level which has the values of: • Note, • Warning, • Error, • and Failure. (Default se-verity level: Error) • In some VHDL system, unsatisfied conditions of severity Error or Failure cause the simulation to terminate.

12. Using Assertions to Specify Timing Requirements • Assertion statements can be used to specify timing requirements, such as set-up time and hold time. • Example If this condition is false report is printed If data is NOT stable and clock=1 then check if clock is stable in hold time When data changes during clock=1 it cannot change during hold time from clock change, this is OK because it changed after hold_time

13. Signal related attributes

14. Pre-defined Signal Attributes

15. Signal Attributes event and last_value

16. Short definitions of these and others Signal Attributes • SIGNAL’event - returns True if an event occurred on this signal during this delta • SIGNAL’active - returns True if a transaction occurred this delta • SIGNAL’last_event - returns the elapsed time since previous event • SIGNAL’last_value- returns previous value of signal before last event • SIGNAL’last_active - returns time elapsed since previous transaction

17. Signal Attributes that return Signals • Delayed(t), Stable, Quiet and transaction

18. Stable Attribute Signal’stable(time) creates a signal that is True when the reference signal has no events for time value

19. Derived signal attribute

20. Signal -Related Attributes • VHDL contains a number of predefined attributes which are related to signals. • They can be divided into two classes: • attributes which define signals themselves • attributes which are functions to provide information about signals. These attributes are signals themselves

21. Examples of Using Attributes: Detecting Edges We use attribute event

22. Measuring Pulse Width

23. Measuring Pulse Width (cont)

24. Measuring Setup Time

25. Delay Parameterization

26. Delay Parameterization • Entities can be made parameterized by the use of • GENERIC CONSTANTS • They are passed to an instantiated component by its environment • A generic constant can be used in computation, but remains fixed during simulation.

27. Delay Parameterization- Structured Example

28. Data Flow Descriptions in VHDL • A data flow description consists of a set of concurrent signal assignment statements. • A signal assignment statement executes in response to change on its input signals.

29. Data Flow Descriptions in VHDL • Each value in the waveform will be scheduled to appear • on the target after the specified delay. • • If the assignment statement executes again, previously • scheduled values may be overridden. • • A delay of zero represents an infinitesimally small delay • signal assignment never takes effect immediately. • • Data flow descriptions are similar to register-transfer • level expressions. • • They may imply hardware implementation structure.

30. Simple data-flow example:

31. More examples of Concurrent Signal Assignment Guarded will be discussed in a separate lecture

32. More examples: Concurrent Signal Assignment • This describes a decoder, or translator from binary to one-hot code We discussed it but now we add timing

33. Conditional Signal Assignment

34. Selected Signal Assignment concatenation

35. For students to use and think about • What is the basic timing model for simulation in VHDL. • Types of delay in VHDL: • transport, • inertial • delay. • Detailed explanation of delta model. Why previous models were inconvenient? The student should be able to assume delta delay draw the timing diagram and next go with delta to zero and illustrate graphically the results of simulation.

36. For students to use and think about • General assignment statements with bit selections, concatenations, timing delays and expressions. • Variables versus signals in assignment statements. • Some selected signal-related attributes. • Conditional signal assignment with when. • Concurrent signal assignment with when • Explain simulation with four-valued simulator. • Assertion statements. • Detailed D FF with timing. • Tri-state buffer and its simulation.

37. Questions for students • Example: MUX • This example highlights the difference between signals and variables ARCHITECTURE test2 OF mux IS SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, y) VARIABLE x : BIT := '1'; BEGIN x := in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test2; ARCHITECTURE test1 OF mux IS SIGNAL x : BIT := '1'; SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, x, y) BEGIN x <= in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test1; • Assuming a 1 to 0 transition on in_sig, what are the resulting values for y in the both cases?

38. Sources • VLSI. Ohio University, Starzyk • Krzysztof Kuchcinski • Yingtao Jiang • Hai Zhou • Prof. K. J. Hintz