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Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Data Flow Modeling of Combinational Logic. Required reading. S. Brown and Z. Vranesic , Fundamentals of Digital Logic with VHDL Design Chapter 6, Combinational-Circuit Building Blocks (sections 6.6.5-6.6.7 optional)

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Data Flow Modeling of Combinational Logic

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  1. ECE 448 Lecture 3 Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL

  2. Required reading • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design • Chapter 6, Combinational-Circuit Building • Blocks (sections 6.6.5-6.6.7 optional) • Chapter 5.5, Design of Arithmetic Circuits • Using CAD Tools ECE 448 – FPGA and ASIC Design with VHDL

  3. Optional Reading • Sundar Rajan, Essential VHDL: RTL Synthesis • Done Right • Chapter 3, Gates, Decoders and Encoders • (see errata at http://www.vahana.com/bugs.htm) ECE 448 – FPGA and ASIC Design with VHDL

  4. Recommended reading Material covered next week and required during the second lab experiment • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design • Chapter 7, Flip-Flops, Registers, Counters, • and a Simple Processor • (7.14 optional) ECE 448 – FPGA and ASIC Design with VHDL

  5. Register Transfer Level (RTL) Design Description Combinational Logic Combinational Logic Today’s Topic … Registers ECE 448 – FPGA and ASIC Design with VHDL

  6. Describing Combinational Logic Using Dataflow Design Style ECE 448 – FPGA and ASIC Design with VHDL

  7. VHDL Design Styles dataflow VHDL Design Styles structural behavioral Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Test benches ECE 448 – FPGA and ASIC Design with VHDL

  8. Synthesizable VHDL Dataflow VHDL Design Style VHDL code synthesizable Dataflow VHDL Design Style VHDL code synthesizable ECE 448 – FPGA and ASIC Design with VHDL

  9. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  10. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  11. Data-flow VHDL: Example ECE 448 – FPGA and ASIC Design with VHDL

  12. Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (x : IN STD_LOGIC ; y: IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ECE 448 – FPGA and ASIC Design with VHDL

  13. Data-flow VHDL: Example (2) ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END fulladd_dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  14. Logic Operators • Logic operators • Logic operators precedence and or nand nor xor not xnor only in VHDL-93 Highest not and or nand nor xor xnor Lowest ECE 448 – FPGA and ASIC Design with VHDL

  15. No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ; ECE 448 – FPGA and ASIC Design with VHDL

  16. Arithmetic Operators in VHDL (1) To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; or USE ieee.std_logic_signed.all; ECE 448 – FPGA and ASIC Design with VHDL

  17. Arithmetic Operators in VHDL (2) You can use standard +, -, * operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B; ECE 448 – FPGA and ASIC Design with VHDL

  18. 16-bit Unsigned Adder 16 16 X Y Cout Cin S 16 ECE 448 – FPGA and ASIC Design with VHDL

  19. VHDL code for a 16-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  20. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  21. Conditional concurrent signal assignment Value N … Value N-1 Target Signal Value 2 Value 1 Condition N-1 Condition 2 Condition 1 When - Else target_signal <= value1whencondition1else value2whencondition2else . . . valueN-1whenconditionN-1else valueN; 0 1 .… 0 1 0 1 ECE 448 – FPGA and ASIC Design with VHDL

  22. Operators • Relational operators • Logic and relational operators precedence = /= < <= > >= Highest not = /= < <= > >= and or nand nor xor xnor Lowest ECE 448 – FPGA and ASIC Design with VHDL

  23. Priority of logic and relational operators compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … ECE 448 – FPGA and ASIC Design with VHDL

  24. VHDL operators ECE 448 – FPGA and ASIC Design with VHDL

  25. 2-to-1 Multiplexer s f s w w 0 0 0 0 f w 1 w 1 1 1 (b) Truth table (a) Graphical symbol ECE 448 – FPGA and ASIC Design with VHDL

  26. VHDL code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  27. Tri-state Buffer – example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 downto 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END tri_state; ECE 448 – FPGA and ASIC Design with VHDL

  28. Tri-state Buffer – example (2) ARCHITECTURE tri_state_dataflow OF tri_state IS BEGIN output <= input WHEN (ena = ‘0’) ELSE (OTHERS => ‘Z’); END tri_state_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  29. 4-bit Number Comparator 4 A AeqB AgtB 4 B AltB ECE 448 – FPGA and ASIC Design with VHDL

  30. VHDL code for a 4-bit UnsignedNumber Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  31. VHDL code for a 4-bit SignedNumber Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  32. Priority Encoder w w w w y y z 3 2 1 0 1 0 0 0 0 0 d d 0 0 0 0 1 0 0 1 x 0 0 1 0 1 1 x x 0 1 1 0 1 x x x 1 1 1 1 w 0 y 0 w 1 y 1 w 2 z w 3 ECE 448 – FPGA and ASIC Design with VHDL

  33. VHDL code for a Priority Encoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  34. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  35. Selected concurrent signal assignment With –Select-When withchoice_expressionselect target_signal <= expression1whenchoices_1, expression2whenchoices_2, . . . expressionNwhenchoices_N; choices_1 expression1 expression2 choices_2 target_signal expressionN choices_N choice expression ECE 448 – FPGA and ASIC Design with VHDL

  36. Allowed formats of choices_k WHEN value WHEN value_1 to value_2 WHEN value_1 | value_2 | .... | value N ECE 448 – FPGA and ASIC Design with VHDL

  37. Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", b WHEN "011" to "110", c WHEN "001" | "111", d WHEN OTHERS; ECE 448 – FPGA and ASIC Design with VHDL

  38. 4-to-1 Multiplexer s 0 s s s f 1 1 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 11 3 w 1 1 3 (a) Graphic symbol (b) Truth table ECE 448 – FPGA and ASIC Design with VHDL

  39. VHDL code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  40. 2-to-4 Decoder w w y y y y En 1 0 0 1 2 3 w y 0 0 0 0 0 1 0 0 1 w y 1 1 0 1 0 1 0 0 1 y 2 1 1 0 0 0 1 0 y En 3 1 1 1 0 0 0 1 x x 0 0 0 0 0 (a) Truth table (b) Graphical symbol ECE 448 – FPGA and ASIC Design with VHDL

  41. VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  42. MLU Example ECE 448 – FPGA and ASIC Design with VHDL

  43. MLU: Block Diagram ECE 448 – FPGA and ASIC Design with VHDL

  44. MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mlu; ECE 448 – FPGA and ASIC Design with VHDL

  45. MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L:STD_LOGIC_VECTOR(1 DOWNTO 0); ECE 448 – FPGA and ASIC Design with VHDL

  46. MLU - Architecture Body BEGIN A1<=NOT A WHEN (NEG_A='1') ELSE A; B1<=NOT B WHEN (NEG_B='1') ELSE B; Y<=NOT Y1 WHEN (NEG_Y='1') ELSE Y1; MUX_0<=A1 AND B1; MUX_1<=A1 OR B1; MUX_2<=A1 XOR B1; MUX_3<=A1 XNOR B1; L <= L1 & L0; with (L) select Y1<=MUX_0 WHEN "00", MUX_1 WHEN "01", MUX_2 WHEN "10", MUX_3 WHEN OTHERS; END mlu_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  47. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  48. For Generate Statement For - Generate label:FORidentifier IN rangeGENERATE BEGIN {Concurrent Statements} END GENERATE; ECE 448 – FPGA and ASIC Design with VHDL

  49. PARITY Example ECE 448 – FPGA and ASIC Design with VHDL

  50. PARITY: Block Diagram ECE 448 – FPGA and ASIC Design with VHDL

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