Amit Berman

1. Reliable Architecture for Flash Memory Amit Berman Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar Department of Electrical Engineering, Technion – Israel Institute of Technology

2. Agenda • Reliability in Flash Memory • “Reliable Architecture” • The advantages of “Reliable Architecture” • Density • Performance • Conclusions

3. Level Level - - 1 1 Introduction • Reliability: a crucial factor in flash memory design • Quantification: Guaranteed # of times that a memory cell can be written and erased before an error occurs • Basic physical characteristic of flash memory cell: every write/erase • operation, the memory cell is degraded • Eventually, there would be a data error in the memory cell, proportional • to the number of write/erase operations Our goal is to reduce the number of physical write/erase operations of the flash memory cells Analogy : Flash memory cell as a glass of water • The amount of water in the glass represents the information • Each time we will fill and empty the glass – it will be cracked Level - 1

4. Level Level Level - - - 3 3 3 Level Level - - 2 2 Level Level - - 1 1 Level Level - - 0 0 Reliability is important for density • Good reliability high density • Bad reliability low density “fewer glass cracks, low water leakage”  we can distinguish between more levels Full Level Level - - 3 3 Level Level - - 2 2 Level Level - - 1 1 Empty Level Level - - 0 0 2 bits per cell (2BPC) 1 bit per cell (1BPC) 11 10 01 00 :Bit 1 0 :Bit 0 1 2 3 :Level Erased Programmed :Level # of cells # of cells Vt Vt Increase density  decrease reliability Ref Ref2 Ref3 Ref1 Reliable Architecture technique increase the reliability We can use it to increase the density and keep constant reliability

5. Level Level Level Level - - - - 2 2 2 2 Level Level Level Level Level Level Level Level - - - - - - - - 0 0 0 0 0 0 0 0 Reliability is important for performance • Bad reliability low writing speed • Good reliability high writing speed “glass cracks makes it hard to fill it” Level Level - - 2 2 Level Level - - 2 2 Level Level - - 0 0 Level Level - - 0 0 11 10 01 00 :Bit 11 10 01 00 :Bit 0 1 2 3 :Level 0 1 2 3 :Level # of cells # of cells Vt Vt Ref2 Ref3 Ref2 Ref3 Ref1 Ref1

6. Related Work • Coding * M. Schwartz, S. Bruck “Rank Modulation for Flash Memories” • MFG Process * M. Yanai, I. Bloom “NROM memory cell design”

7. Observation • Flash data is erased in blocks (e.g. 64KB) • The memory needs to be erased in order to write new information • Erase operation lasts long (e.g. 1.5mS)  cells are erased in groups erase • There are redundant write and erase operations erase write The cell returned to its original level

8. Observation: Example • There are redundant write and erase operations Time At time T1, information is written T1 Vt Block is erased to enable new write T2 Vt New write is same as the initial value T3 Vt In this process there are total 2 writes and 1 erase operations, can we reduce it to 1 write operation? 8

9. Reliable Architecture • New concept of operating flash memory Common Architecture vs. Reliable Architecture Write Re-write Erase Virtual Erase Read (no change)

10. Re-write concept Flash Re-write Concept read the stored data, compare it to the input data and adjust for the difference if exists read and adjust If equal: do nothing If difference: adjust

11. I/O Analog HV Non-Volatile Memory Array Control Logic Spare NVM Valid Indication Virtual erase concept • Construct a “spare memory array” that contain information about erase status • Virtual erase process: when erase is applied to a certain block/page • Mark a flag in the spare memory array for erase indication • Data is not physically erased erase virtual erase flag flag

12. Reliable Architecture: changes to the current architecture • Target: Avoid redundant write and erase operations • Changes: Arrange the memory array so that erase in a single cell is enabled Change the control logic for the new operations Add spare memory cells for virtual erase operation

13. Analysis : symmetric binary source While applying memory write, average # of cells with no transition: NT=# of bits with no transition l= # of flash memory levels n= # of bits in a page Average # of cells with write transition: Average # of cells with erase transition:

14. Example For 2-levels flash with random input data source: • Each writing operation 50% of the memory cells hold the same value 25% of the memory cells have write transition 25% of the memory cells have erase transition  Saves 50% of write/erase operations, x2 improvement * Taking into account Gaussian distribution

15. Reliability Improvement Factor (RIF) while using Reliable Architecture RIF is lower bound since we also save some transitions between levels

16. Performance analysis • Reliable architecture has advantage in large page size: Erase Operation ~1.5ms Erase can be done in parallel, for any # of memory cells Write Operation ~0.8ms Writing is done sequentially due to current consumption limitations (2KB page) • The Reliable Architecture re-write concept uses the erase operation on some of the cells • On small page size, the erase transition reduce performance • In a large page size, the write performance is better then the one in common architecture

17. Performance analysis • Modeling results of flash memory cells, write and erase operations with varying page size, utilizing a symmetric data source *MATLAB Reliable Architecture is effective in large page size (>8KB)

18. Summary • Reliable Architecture statistically improves flash memory reliability • Can be used to increase reliability • Can be use to increase density and keep reliability constant • Reliable Architecture improves reliability by the elimination of the redundant write/erase operations to the flash memory • Reliable Architecture is improving the write performance in page size >8KB in a smaller page size, write performance is reduced

19. Questions? High Density Low $/MB ROM DRAM EPROM SRAM FLASH Updateable EEPROM Nonvolatile