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Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [Comment resolutions for FEC] Date Submitted: [November 10 , 2010] Source: [Daniel Popa] Company [ Itron , Inc] Address [France] E-Mail: [daniel.popa@itron.com] Re: []

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Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

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  1. Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [Comment resolutions for FEC] Date Submitted: [November 10 , 2010] Source:[Daniel Popa] Company [Itron, Inc] Address [France] E-Mail: [daniel.popa@itron.com] Re: [] Abstract: [Resolutions to comments for MR-FSK FEC] Purpose: [This document provides resolutions to FEC comments of LB #59] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15.

  2. CID 462 • Comment: • Figure 65q should show the outputs as "u sub i super 0 and u sub i super 1". Label should indicate that PAD bits are not shown. A bus symbol showing that the output of the Tail bit inserter is 3 wide should be included. • Commenter request resolution • Check • Response: N/A • Proposed resolution: Defer it.

  3. CID 704 • Comment: • Table 75d contains a wrong heading for memory state. Some sequences of this column seem to be not correct with regard to RSC (T0 T1 T2). • Commenter requested resolution: • Correct heading to (M0-M2). It appears all sequences of this column need to be time reversed. • Response: N/A • Proposed resolution: Defer it.

  4. CID 835 • Comment: • Sentence says “Each bit shall be processed through the concatenator, FEC, data whitening, and modulation functions using bit order rules defined in 6.3a.” • FEC and data whitening are optional. • Commenter requested resolution • Remove the sentence, as it is not necessary. • Response:6.3a does not clearly state if/that the bit rules defined in this section shall apply to the processing done in all (functional) blocks that forms a MR-FSK PHY. Editors to fix it. • Proposed resolution: Accept in principle.

  5. CID 839 • Comment: • The text beginning "An interleaving scheme…" is redundant. The text on lines 36-38 say this already. • Commenter requested resolution • Remove text on lint 51. Add cross ref to 6.12a.1.5 to the text on lines 36-38. • Response: N/A • Proposed resolution: Accept.

  6. CID 990 • Comment: • The formula "j = ii * (NINTERLEAV/2) -1" is not correct. • Commenter requested resolution • Replace it with "j = (ii+1) * (NINTERLEAV/2) -1“. • Response: It seems to be an editorial error. Editors to correct the error. • Proposed resolution: Accept.

  7. CID 1092 • Comment: • Require example frame FEC encoded, before and after encoding. One each for RSC and NRNSC. • Commenter requested resolution • Insert after Line 14 example of inputs and outputs for RSC and NRNSC FEC encoding mechanisms • Response: Add an informative annex with an example. • Proposed resolution: Accept.

  8. CID 1093 • Comment: • Require example input frame to interleaver with resulting output. • Commenter requested resolution • Insert after Line 39 an example of input and output frame to interleaver of resulting output. • Response: Add an informative annex with an example. • Proposed resolution: Accept.

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