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ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game. Agenda for today. Part 1: Distribution of FPGA boards Part 2: Diagnostics of FPGA boards Part 3: Introduction to FPGA Design Flow based on Aldec Active-HDL Part 4: Introduction to Lab 5

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ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

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  1. ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

  2. Agenda for today Part 1: Distribution of FPGA boards Part 2: Diagnostics of FPGA boards Part 3: Introduction to FPGA Design Flow based on Aldec Active-HDL Part 4: Introduction to Lab 5 Part 5: Demos of Lab 4 & late demos of Lab 3

  3. Parts 1 & 2 Distribution and Diagnostics of FPGA Boards

  4. Part 3 Hands-on Session on FPGA Design Flow based on Aldec Active-HDL

  5. Part 4 Introduction to Lab 5

  6. Task 1 Experimental Testing of Lab 4 for Task 5 & Lab 4 for Task 6

  7. LAB4 for TASK5 BTNL BTNL BTNR BTNU BTND BTNS SW CLOCK BTNR 8 clk BTNL BTNR BTNU BTND BTNS SW rst BUTTON_UNIT next_out SWITCH_UNIT CLK_RST_1 loadA loadB step run 8 8 rst clk loadA loadB step run IVA IVB clk LAB3e rst rst XSGN YSGN Xout Yout Aout Bout k clk 10 8 8 8 8 8 8 XSGN YSGN X Y A B k hex0 4 hex0 clk SSD_DRIVER 4 hex1 hex1 TASK5 4 hex2 hex2 rst 4 LED hex3 hex3 SEG AN 8 4 7 LED SEG AN

  8. step run loadA IVA loadB IVB loadB loadA 8 8 OR cnz en en nexti nexti ld ld OR OR nexto LFSR LFSR clk clk rst rst rst rst clk clk AND not done AND X”00” X”00” 8 8 en CNTR UP nexto 0 0 1 1 rst rst cnz cnz clk clk 8 8 k 10 A B = X”3FF” 10 k9..8 sel 2 8 done k7..0 LAB2 ≠ 0 En ‘0’ cnz X Y 8 8 LAB3e en nexto en nexto rst rst rst MISR rst MISR clk clk A B k clk clk 10 8 8 8 8 8 8 8 XSGN Xout Aout YSGN Yout Bout kout

  9. BUTTON_UNIT rst rst BTNL loadA Debouncer RED rst clk clk rst rst BTNR loadB Debouncer RED clk clk clk rst rst BTNU step Debouncer RED clk clk rst rst BTND next_out Debouncer RED rst clk clk run rst ‘1’ Q D BTNS en Debouncer RED clk clk

  10. Debouncer rst clk

  11. Generics of the Debouncer k – size of the counter DD – debouncing period in clock cycles Please make sure that: DD  TCLK ≈ 10 ms 2k > DD

  12. Rising Edge Detector - RED rst input output clk

  13. SWITCH_UNIT 8 8 SW IVA 8 IVB

  14. SSD_DRIVER SEG(6..0) Counter UP Counter UP q(k-1..k-2) Counter UP COUNTER UP Counter UP clk AN OC Counter UP rst OC – One’s Complement

  15. Multiplexing Digits

  16. Generics of the SSD_DRIVER k – size of the internal counter. Refresh period = 2k clock cycles. 1 ms ≤ Refresh period ≤ 16 ms 1 ms ≤ 2k TCLK ≤ 16 ms fCLK = 100 MHz k = ?

  17. CLK_RST_1 CLOCK clk BTNL rst BTNR

  18. LAB4 for TASK6 BTNL BTNL BTNR BTNU BTND BTNS SW CLOCK BTNR 8 clk BTNL BTNR BTNU BTND BTNS SW rst BUTTON_UNIT next_out SWITCH_UNIT CLK_RST_2 loadA loadB step run 8 8 rst clk loadA loadB step run IVA IVB clk LAB3e rst rst XSGN YSGN Xout Yout Aout Bout k clk 10 8 8 8 8 8 8 XSGN YSGN X Y A B k hex0 4 hex0 clk SSD_DRIVER 4 hex1 hex1 TASK5 4 hex2 hex2 rst 4 LED hex3 hex3 SEG AN 8 4 7 LED SEG AN

  19. CLK_RST_2 ‘0’ clkfx_obufg clkfx DCM_SP BUFG 0 clkfx clk clk_ibufg clk0_obufg clk100 IBUFG CLOCK clkin clk0 BUFG 1 BUFGMUX BTNL rst_or rst BTNR rst clkfb locked

  20. Task 2 Verifying Maximum Experimental Clock Frequency

  21. CLK_RST_3 CLOCKFX CLOCK100 SW(0) ODDR2 Q ODDR2 Q D0 D1 C0 C1 CE R S D0 D1 C0 C1 CE R S ‘1’‘0’‘1’‘0’‘0’ ‘1’‘0’‘1’‘0’‘0’ clkfx clkfx_180 clk100 clk100_180 BUFGMUX clkfx_obufg clkfx BUFG 0 clkfx clk clk_ibufg clk0_obufg clk100 IBUFG CLOCK clkin clk0 BUFG 1 clk180_obufg clk180 BUFG BTNL rst_or clk100_180 rst clkfx180_obufg BTNR clkfx180 BUFG clkfb clkfx_180 locked rst

  22. LAB5 for TASK2 BTNL BTNL BTNR BTNU BTND BTNS SW SW(0) CLOCK BTNR 8 clk BTNL BTNR BTNU BTND BTNS SW rst BUTTON_UNIT next_out SWITCH_UNIT CLK_RST_3 loadA loadB step run 8 8 rst clk loadA loadB step run IVA IVB clk CLOCK100 LAB3e CLOCKFX rst rst XSGN YSGN Xout Yout Aout Bout k clk 10 8 8 8 8 8 8 XSGN YSGN X Y A B k hex0 4 hex0 clk SSD_DRIVER 4 hex1 hex1 TASK5 4 hex2 hex2 rst 4 LED hex3 hex3 SEG AN 8 4 7 LED SEG AN

  23. Verifying Maximum Clock Frequency The circuit should work correctly for SW(0) = 1 => clk = clk100 => fCLK = 100 MHz The circuit should fail for SW(0) = 0 => clk = clkfx => fCLK > maximum fCLK

  24. Setting frequency of clkFX during DCM_SP Instantiation DCM_SP_inst : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- CLKDV divide value -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). -- Divide value on CLKFX outputs - D - (1-32) -- Multiply value on CLKFX outputs - M - (2-32) -- CLKIN divide by two (TRUE/FALSE) -- Input clock period specified in nS -- Output phase shift (NONE, FIXED, VARIABLE) -- Feedback source (NONE, 1X, 2X) CLKFX_DIVIDE => …………., CLKFX_MULTIPLY => ………, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 10.0, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X”,

  25. Observing CLOCK100 and CLOCKFXusing Oscilloscope • Using oscilloscope and two versions of your implementation • (with different values of generics of DCM_SP) • show the clock signal for the following three cases: • fCLK = 100 MHz • fCLK = maximum clock frequency returned by the tools • fCLK = 10 MHz • Document your findings using digital photos. • Discuss your observations.

  26. New Lines in theUser Constraint File (UCF) NET "CLOCK100" LOC = "…….." | IOSTANDARD = "LVCMOS33"; NET "CLOCKFX" LOC = "…….." | IOSTANDARD = "LVCMOS33”; Select two arbitrary board pins that would be the most easy to observe, and have a relatively large physical distance from each other (to avoid interference).

  27. Task 3 Fast Reflex Game

  28. Rules of the Game (1) BCD Counter is initialized with 10.00 seconds. After pressing start_stop the counter starts counting down every 0.01 second: 9.99, 9.98, 9.97, …, 0.02, 0.01, 0.00, -0.01, -0.02 … The goal is to press the start_stop button again as close as possible to 0.00. After the second press, the counter is stopped.

  29. Rules of the Game (2) The last obtained result can be a. stored with the press of the store button b. skipped with the press of the skip button. After performing these operations the counter is again initialized to 10.00. Only the last 4 stored results are remembered by the system. The minimum and the maximum absolute value of these last 4 stored results is calculated. The clear button clears the storage, and initializes the counter to 10.00.

  30. Meaning of Buttons BTNU store BTNL BTNS BTNR clear start_stop next_out BTND skip

  31. Rules of the Game (3) The next_out button allows displaying 1. current value of the counter 2. the last stored result 3. the result with the minimum absolute value 4. the result with the maximum absolute value. After each press of the next_out button, the mode of display changes to the next one in the wrap-around fashion. The current mode is also indicated with an appropriate number of the rightmost LEDs turned on (1 for the current value of the counter, 2 for the last stored result, etc.)

  32. 4-digit BCD Counter Down BCD_CD rst clk minimum init minimum = 1  Counter = -9.99 clk minus X”1” init minus X”0” init minus X”0” init minus X”0” init 4 4 4 4 dir dir dir dir ld ld ld ld rst CD_mod_9 CD_mod_9 CD_mod_9 CD_mod_9 b(0)=bin b(1) b(2) b(3) b(4) set bout bout bout bout en en en en clk clk clk clk rst rst rst rst DFF rst rst rst rst 4 4 4 4 minus D(3) D(2) D(1) D(0) dir = 0 : count down dir = 1 : count up CD_mod_9 – Counter Down mod 9 bin – borrow in bout – borrow out

  33. Result Storage & Processing - RSP result store rst clk 13 rst en rst REG clk last last 13 rst en rst REG clk MIN ABS MAX ABS 13 max min rst en rst REG clk 13 rst en rst REG clk 13 min last max result MAXABS – Maximum Absolute Value 0 1 2 3 MINABS – Minimum Absolute Value 2 13 output sel_out

  34. BUTTON_UNIT rst rst BTNL clear Debouncer RED rst clk clk rst rst BTNR next_out Debouncer RED clk clk clk rst rst BTNU store Debouncer RED clk clk rst rst BTND skip Debouncer RED clk clk rst BTNS start_stop Debouncer RED clk

  35. CLK_RST_4 CLOCK clk BTNL rst BTND

  36. Top-Level of Fast Reflex Game init 0 CONTROLLER k rst clk rst count ld en minimum BUTTON_UNIT CU_mod_N minimum BCD_CD clk cdown init cout init bin rst clear next_out store skip start_stop minus & D(2..0) D(3) rst BTNL BTNR BTNU BTND BTNS count BTNL 4 BTND CLOCK 13 D3 clear_res result clear_res store_res rst store CLK_RST_4 RSP clk sel_out sel_out clk rst 2 output rst D3 13 rst clk 4 rst clk rst sel_out hex0 hex0 4 SSD_DRIVER hex1 4 hex1 OUT_FORMAT 4 hex2 hex2 4 rst rst hex3 hex3 SEG AN LED clk 4 8 8 SEG AN LED CU_mod_N: Counter Up mod N

  37. Part 5 Demos of Lab 4 & Late Demos of Lab 3

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