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ELEN468 Advanced Logic Design

ELEN468 Advanced Logic Design. Lecture 1 Introduction. Chips Everywhere!. What are inside a chip?. A chip may include: Hundreds of millions of transistors ~Mb embedded SRAM DSP, IP cores PLL, ADC, DAC… 100+ internal clocks … … Design issues: Speed Power Area Signal integrity

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ELEN468 Advanced Logic Design

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  1. ELEN468 Advanced Logic Design Lecture 1 Introduction ELEN468 Lecture 1

  2. Chips Everywhere! ELEN468 Lecture 1

  3. What are inside a chip? • A chip may include: • Hundreds of millions of transistors • ~Mb embedded SRAM • DSP, IP cores • PLL, ADC, DAC… • 100+ internal clocks • … … • Design issues: • Speed • Power • Area • Signal integrity • Process variation • Manufacturing yield • … … Source: Byran Preas ELEN468 Lecture 1

  4. Technology (nm) 115 90 65 45 32 22 Year 2002 2004 2007 2010 2013 2016 # transistors 112M 178M 357M 714M 1427M 2854M Clock freq. (MHz) 2317 3990 6739 11511 19348 28751 Power (W) 140 160 190 218 251 288 Wiring levels 7-8 8 9 9-10 9-10 10 Technology Roadmap for Semiconductors Technology  minimal transistor feature size ELEN468 Lecture 1

  5. Chip Design Productivity Crisis 10,000,000 100,000,000 1,000,000 10,000,000 58%/Yr. Complexity growth rate 100,000 1,000,000 10,000 100,000 Transistor/Staff-Month Transistors/Chip (K) 1,000 10,000 x x 100 1,000 x x x x 21%/Yr. Productivity growth rate x x 10 100 1 10 1998 2003 Source NTRS’97 ELEN468 Lecture 1

  6. Solutions • Apply CAD tools • High level abstraction • Learn Verilog ! ELEN468 Lecture 1

  7. Basic Design Flow System/Architectural Design • System design • Instruction set for processor • Hardware/software partition • Memory, cache • Logic design • Logic synthesis • Logic optimization • Technology mapping • Physical design • Floorplanning • Placement • Routing Logic Design Physical Design/Layout Fabrication ELEN468 Lecture 1

  8. Design Cycles System/Architectural Design HDL Logic Design Verification/Simulation Physical Design/Layout Parasitic Extraction Fabrication Testing ELEN468 Lecture 1

  9. Design and Technology Styles • Custom design • Mostly manual design, long design cycle • High performance, high volume • Microprocessors, analog, leaf cells, IP … • Standard cell • Pre-designed cells, CAD, short design cycle • Medium performance, ASIC • FPGA/PLD • Pre-fabricated, fast automated design, low cost • Prototyping, reconfigurable computing ELEN468 Lecture 1

  10. Why do we need HDLs ? • HDL can describe both circuit structure and behavior • Schematics describe only circuit structure • C language describes only behaviors • Provide high level abstraction to speed up design • High portability and readability • Enable rapid prototyping • Support different hardware styles ELEN468 Lecture 1

  11. What do we need from HDLs ? • Describe • Combinational logic • Level sensitive storage devices • Edge-triggered storage devices • Provide different levels of abstraction and support hierarchical design • System level • RTL level • Gate level • Transistor level • Physical level • Support for hardware concurrency ELEN468 Lecture 1

  12. Two major HDLs • Verilog • Slightly better at gate/transistor level • Language style close to C/C++ • Pre-defined data type, easy to use • VHDL • Slightly better at system level • Language style close to Pascal • User-defined data type, more flexible • Equally effective, personal preference ELEN468 Lecture 1

  13. a sum Add_half b c_out Schematic Design a sum b c_out_bar c_out sum = a  b c_out = a • b ELEN468 Lecture 1

  14. Module name Module ports Declaration of port modes Declaration of internal signal Instantiation of primitive gates Verilog keywords Taste of Verilog module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule a sum b c_out_bar c_out ELEN468 Lecture 1

  15. a sum Add_half b c_out Behavioral Description module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; reg sum, c_out; always @ ( a or b ) begin sum = a ^ b; // Exclusive or c_out = a & b; // And end endmodule ELEN468 Lecture 1

  16. rst data_in q clk Declaration of synchronous behavior Procedural statement Example of Flip-flop module Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; always @ ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; end endmodule ELEN468 Lecture 1

  17. Conclusion • VLSI Chips • Chip design flow • Chip design styles • Why do we need HDLs ? • What do we need from HDLs ? • Examples of Verilog HDL ELEN468 Lecture 1

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