1 / 32

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva and S. Ramesh LSI Logic Corporation. Outline.

orien
Télécharger la présentation

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva and S. Ramesh LSI Logic Corporation

  2. Outline • Products need very high-density and high-performance memories without sacrificing yield and manufacturability • LSI Logic’s Industry-leading 1.87um2 embedded SRAM bitcell in 130 nm CMOS SoC technology • Need for SRAM-specific test structures to ensure robustness and manufacturability • Accurately shows process-design interaction • Correlate to SRAM yield • Direct feedback for rapid process-improvement • Accurate SRAM device and cell characterization • RAMPCM for design rule robustness validation • Summary ISQED-2003

  3. LSI Logic SRAM Technology for SoC • Smallest production high-density SRAM in 180nm and 130nm technology • Fabricated by standard CMOS SoC process “High-Density and High-Performance 6T-SRAM for System-on-Chip in130 nm CMOS Technology,” 2001 VLSI Technology Symposium, pp. 105-106, W. Kong, R. Venkatraman, R. Castagnetti, F. Duan and S. Ramesh. ISQED-2003

  4. Why Do We Need for SRAM-specific Test Structure? An Example (a) (b) (c) Structures to test metal bridging ISQED-2003

  5. Electrical Test Data Only structure (a) detects the early metal /contact bridging ISQED-2003

  6. Features of Our Structures • Compared to the conventional structures, our structures: • More product-driven than process-development-driven • Accurately show process-design interaction • Correlate to functionality and yield directly • Identify the yield limiting factors quickly for fast process or design improvements. • Sensitive enough for ongoing monitoring and process transfers. ISQED-2003

  7. Test Structure Design and Results • Yield correlation and improvement • SRAM manufacturability • SRAM device and cell characterization • RAMPCM chip • Functional SRAM test chip • Used for SRAM design rule validation ISQED-2003

  8. Test Structures of Front-end Critical Layer Monitor • Critical layers: island, poly and contact • Monitor bridging current from intra- and inter- layers • Monitor shared-contact connection ISQED-2003

  9. Test Structures of Back-end Monitor • Monitor bridging current from: • Contact and metal 1 (blue arrows) • Metal 2 (red arrows) • Metal 3 (black arrow) ISQED-2003

  10. Example of a Test Structure For Poly Bridging Test array Test cell ISQED-2003

  11. Poly Bridging Data 100,000 cells No poly bridging found in SRAM ISQED-2003

  12. Metal Bridging and Correlation to SRAM Yield 100,000 cells Detected early metal /contact bridging ISQED-2003

  13. Metal Bridging and Correlation to SRAM Yield (cont.) Metal bridging identified as yield limiting factor ISQED-2003

  14. Metal 1 Bridging Data after Process Improvement 100,000 cells No metal bridging seen after improvement ISQED-2003

  15. Test Structures for Manufacturability • An illustration of test structure • List of test structures • Electrical data ISQED-2003

  16. An Illustration of the Test Structure • Sizing poly by 5% per side • Build test cell to test its effects on: • Poly to poly bridging • Poly to contact bridging • Pull down transistor leakage ISQED-2003

  17. List of Test Structures for SRAM Manufacturability • Sizing island • Island to island bridging • Transistor leakage • Sizing poly • Poly to poly bridging • Poly to contact bridging • Transistor leakage • Sizing contact • Contact to poly bridging • Contact / metal 1 bridging • Contact resistance • Sizing metal 1 • Metal 1 / contact bridging ISQED-2003

  18. Effect of Poly Sizing – SRAM Poly to Poly Bridging 100,000 cells Poly to poly spacing in SRAM is robust ISQED-2003

  19. Effect of Poly Sizing – SRAM Poly to Contact Bridging 100,000 cells Poly to contact spacing in SRAM is robust ISQED-2003

  20. Effect of Poly Sizing – SRAM Pull Down Transistor Leakage 100,000 cells All leakage currents are within device model spec ISQED-2003

  21. Test Structures for Characterization • Transistors in SRAM • Due to the environmental difference (OPC, etc), transistors in SRAM may behave differently compared to isolated devices • Need to measure transistor in the real SRAM array for accurate characterization • An illustration of test structures • Electrical data for transistor measurement • Cell characterization ISQED-2003

  22. Illustration of Measuring SRAM Transistor ISQED-2003

  23. Transistors in SRAM Cell • Measure all the 6 transistors in 6T SRAM • To compare cell symmetry between left and right • To compare with isolated devices • Measure 4 orientations ISQED-2003

  24. Saturation Current of Pass Gate Transistors (Left, Right, Isolated Counterpart) Good symmetry and little difference between iso. / dense ISQED-2003

  25. Saturation Current of Pull Down Transistors (Left, Right, Isolated Counterpart) Good symmetry and little difference between iso. / dense ISQED-2003

  26. Threshold Voltage of Pull Down Transistor in 4 Directions (0, 90, 180, 270) Little difference of 4 different orientations ISQED-2003

  27. SNM and Cell Current of 1.87 um2 Bitcell(130nm Generation) 0.001 0.003 0.005 0.007 0.009 Cell Current (A) Butterfly curve Cell current (L&R) ISQED-2003

  28. RAMPCM Test Chip • RAMPCM is a functional SRAM test chip that is used to prove robustness of the most critical SRAM design rules. • Size of the chip is 1M with 1024 row by 1024 columns • Every 64 columns evaluate one critical SRAM design rule ISQED-2003

  29. RAMPCM Test Chip (continued) • 8 most critical design rules are evaluated • Each design rule has 4 variations, distributed across array • Data logs from failing dies are used to extract numbers of failing bits per design rule variation ISQED-2003

  30. RAMPCM Test Data -- Normalized Failure Rate Within process window Design rules used in 1.87 um2 cell Note: More than 50Mb data for each variation. This data proves the robustness and manufacturability of the 1.87 um2 bitcell ISQED-2003

  31. Use of Test Structures in 90nm and Beyond • Increased design-process interaction in 90nm and beyond (Ex. OPC variation) • The test structure methodology we have presented today becomes even more necessary for 90 nm and beyond • Gate leakage impact for SRAM must be accurately evaluated • We have designed such necessary test structures for the 90nm node ISQED-2003

  32. Summary • We have designed and used SRAM-specific test structures as effective tool for SRAM technology development. • The data from these SRAM test structures provides us direct feedback on process-design interactions and helps to identify yield-limiting factors early and quickly. • The data (including from RAMPCM) is analyzed to prove the robustness and manufacturability of our industry-leading 1.87 um2 SRAM cell. ISQED-2003

More Related